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shared hardware for AES 64 decode

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This commit is contained in:
David Harris 2024-03-10 23:51:32 -07:00
parent f950067600
commit b53e873a11
5 changed files with 10 additions and 140 deletions
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11
src/ieu/aes_instructions/aes64dsm.sv → src/ieu/aes_instructions/aes64d.sv
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@ -1,10 +1,10 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// aes64dsm.sv // aes64d.sv
// //
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024 // Created: 20 February 2024
// //
// Purpose: aes64dsm instruction: RV64 middle round decryption // Purpose: aes64dsm and aes64ds instruction: RV64 middle and final round AES decryption
// //
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw // https://github.com/openhwgroup/cvw
@ -25,10 +25,11 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module aes64dsm( module aes64d(
input logic [63:0] rs1, input logic [63:0] rs1,
input logic [63:0] rs2, input logic [63:0] rs2,
output logic [63:0] DataOut input logic finalround,
output logic [63:0] result
); );
logic [127:0] ShiftRowOut; logic [127:0] ShiftRowOut;
@ -47,5 +48,5 @@ module aes64dsm(
aesinvmixcolumns invmw1(SboxOut1, MixcolOut1); aesinvmixcolumns invmw1(SboxOut1, MixcolOut1);
// Concatenate mixed words for output // Concatenate mixed words for output
assign DataOut = {MixcolOut1, MixcolOut0}; mux2 #(64) resultmux({SboxOut1, SboxOut0}, {MixcolOut1, MixcolOut0}, finalround, result);
endmodule endmodule

46
src/ieu/aes_instructions/aes64ds.sv
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@ -1,46 +0,0 @@
///////////////////////////////////////////
// aes64ds.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes64ds instruction: RV64 final round decryption
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes64ds(
input logic [63:0] rs1,
input logic [63:0] rs2,
output logic [63:0] DataOut
);
logic [127:0] ShiftRowOut;
logic [31:0] SboxOut0, SboxOut1;
// Apply inverse shiftrows to rs2 and rs1
aesinvshiftrow srow({rs2,rs1}, ShiftRowOut);
// Apply full word inverse substitution to lower 2 words of shiftrow out
aesinvsboxword inv_sbox_0(ShiftRowOut[31:0], SboxOut0);
aesinvsboxword inv_sbox_1(ShiftRowOut[63:32], SboxOut1);
// Concatenate the two substitution outputs to get result
assign DataOut = {SboxOut1, SboxOut0};
endmodule

43
src/ieu/kmu/zknd32.sv
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@ -1,43 +0,0 @@
///////////////////////////////////////////
// zknd32.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 27 November 2023
// Modified: 31 January 2024
//
// Purpose: RISC-V ZKND top level unit for 32-bit instructions: RV32 NIST AES Decryption
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module zknd32 #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, B,
input logic [6:0] Funct7,
input logic [2:0] ZKNDSelect,
output logic [WIDTH-1:0] ZKNDResult
);
logic [31:0] aes32dsiRes, aes32dsmiRes;
// RV32
aes32dsi aes32dsi(.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32dsiRes));
aes32dsmi aes32dsmi(.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32dsmiRes));
mux2 #(WIDTH) zkndmux(aes32dsiRes, aes32dsmiRes, ZKNDSelect[0], ZKNDResult);
endmodule

8
src/ieu/kmu/zknd64.sv
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@ -34,14 +34,14 @@ module zknd64 #(parameter WIDTH=32) (
output logic [WIDTH-1:0] ZKNDResult output logic [WIDTH-1:0] ZKNDResult
); );
logic [63:0] aes64dsRes, aes64dsmRes, aes64imRes, aes64ks1iRes, aes64ks2Res; logic [63:0] aes64dRes, aes64imRes, aes64ks1iRes, aes64ks2Res;
// RV64 // RV64
aes64ds aes64ds(.rs1(A), .rs2(B), .DataOut(aes64dsRes)); // aes64ds aes64ds(.rs1(A), .rs2(B), .DataOut(aes64dsRes));
aes64dsm aes64dsm(.rs1(A), .rs2(B), .DataOut(aes64dsmRes)); aes64d aes64d(.rs1(A), .rs2(B), .finalround(ZKNDSelect[0]), .result(aes64dRes)); // decode AES
aes64im aes64im(.rs1(A), .DataOut(aes64imRes)); aes64im aes64im(.rs1(A), .DataOut(aes64imRes));
aes64ks1i aes64ks1i(.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes)); aes64ks1i aes64ks1i(.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
aes64ks2 aes64ks2(.rs2(B), .rs1(A), .rd(aes64ks2Res)); aes64ks2 aes64ks2(.rs2(B), .rs1(A), .rd(aes64ks2Res));
mux5 #(WIDTH) zkndmux(aes64dsRes, aes64dsmRes, aes64imRes, aes64ks1iRes, aes64ks2Res, ZKNDSelect, ZKNDResult); mux5 #(WIDTH) zkndmux(aes64dRes, aes64dRes, aes64imRes, aes64ks1iRes, aes64ks2Res, ZKNDSelect, ZKNDResult);
endmodule endmodule

42
src/ieu/kmu/zkne32.sv
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@ -1,42 +0,0 @@
///////////////////////////////////////////
// zkne32.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 21 November 2023
// Modified: 31 January 2024
//
// Purpose: RISC-V ZKNE top level unit for 32-bit instructions: RV32 NIST AES Encryption
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module zkne32 #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, B,
input logic [6:0] Funct7,
input logic [2:0] ZKNESelect,
output logic [WIDTH-1:0] ZKNEResult);
logic [31:0] aes32esiRes, aes32esmiRes;
// RV32
aes32esi aes32esi(.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32esiRes));
aes32esmi aes32esmi(.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32esmiRes));
mux2 #(WIDTH) zknemux(aes32esiRes, aes32esmiRes, ZKNESelect[0], ZKNEResult);
endmodule