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format + min/max structural mux

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This commit is contained in:
Kevin Kim 2023-03-20 09:37:57 -07:00
parent 0d0d3b981e
commit b394e343f6
2 changed files with 3 additions and 6 deletions
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4
src/ieu/bmu/zbb.sv
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@ -47,8 +47,8 @@ module zbb #(parameter WIDTH=32) (
byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult));
ext #(WIDTH) ext(.A(A), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult(ExtResult)); ext #(WIDTH) ext(.A(A), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult(ExtResult));
assign MaxResult = (lt) ? B : A; mux2 #(WIDTH) maxmux(A, B, lt, MaxResult);
assign MinResult = (lt) ? A : B; mux2 #(WIDTH) minmux(B, A, lt, MinResult);
// ZBB Result select mux // ZBB Result select mux
mux5 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinResult, MaxResult, ZBBSelect, ZBBResult); mux5 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinResult, MaxResult, ZBBSelect, ZBBResult);

3
src/ieu/controller.sv
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@ -246,13 +246,11 @@ module controller(
assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD; assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD;
assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand
assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source? assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros
assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001);
assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i
// ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra
assign sltuD = (Funct3D == 3'b011); assign sltuD = (Funct3D == 3'b011);
assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi
@ -268,7 +266,6 @@ module controller(
assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ;
end else assign sltD = (Funct3D == 3'b010); end else assign sltD = (Funct3D == 3'b010);
//assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand
end else begin: bitmanipi end else begin: bitmanipi
assign ALUSelectD = Funct3D; assign ALUSelectD = Funct3D;
assign ALUSelectE = Funct3E; assign ALUSelectE = Funct3E;