From b394e343f68ff18aec52d9c892d7adcd9a0fcb2f Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Mon, 20 Mar 2023 09:37:57 -0700
Subject: [PATCH] format + min/max structural mux

---
 src/ieu/bmu/zbb.sv    | 4 ++--
 src/ieu/controller.sv | 5 +----
 2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv
index 70b984ead..ddf96b113 100644
--- a/src/ieu/bmu/zbb.sv
+++ b/src/ieu/bmu/zbb.sv
@@ -47,8 +47,8 @@ module zbb #(parameter WIDTH=32) (
   byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult));
   ext #(WIDTH) ext(.A(A), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult(ExtResult));
 
-  assign MaxResult = (lt) ? B : A;
-  assign MinResult = (lt) ? A : B;
+  mux2 #(WIDTH) maxmux(A, B, lt, MaxResult);
+  mux2 #(WIDTH) minmux(B, A, lt, MinResult);
 
   // ZBB Result select mux
   mux5 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinResult, MaxResult, ZBBSelect, ZBBResult);
diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index 4e20458cd..22c9d0577 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -246,13 +246,11 @@ module controller(
   assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD;
   assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand
   
-
   assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
   assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]);            // Don't write if setting or clearing zeros
   assign SFenceVmaD = PrivilegedD & (InstrD[31:25] ==  7'b0001001);
   assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i
   
-
   // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra
   assign sltuD = (Funct3D == 3'b011); 
   assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);  // OpD[5] needed to distinguish sub from addi
@@ -268,7 +266,6 @@ module controller(
       assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ;
     end else assign sltD = (Funct3D == 3'b010);
 
-    //assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand
   end else begin: bitmanipi
     assign ALUSelectD = Funct3D;
     assign ALUSelectE = Funct3E;
@@ -314,7 +311,7 @@ module controller(
   //  The comparator handles both signed and unsigned branches using BranchSignedE
   //  Hence, only eq and lt flags are needed
   //  We also want comparator to handle signed comparison on a max/min bitmanip instruction
-  assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE) | BComparatorSignedE ;
+  assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE) | BComparatorSignedE;
   assign {eqE, ltE} = FlagsE;
   mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE);
   assign BranchTakenE = BranchFlagE ^ Funct3E[0];