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uncore cleanup

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This commit is contained in:
David Harris 2023-01-14 17:07:36 -08:00
parent ae7e7b57ec
commit b302f66baf
3 changed files with 28 additions and 36 deletions
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32
pipelined/src/uncore/uartPC16550D.sv
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@ -38,29 +38,21 @@
module uartPC16550D(
// Processor Interface
input logic PCLK, PRESETn,
input logic [2:0] A,
input logic [7:0] Din,
output logic [7:0] Dout,
input logic MEMRb, MEMWb,
output logic INTR, TXRDYb, RXRDYb,
input logic CLK, PRESETn, // UART clock and active low reset
input logic [2:0] A, // address input (8 registers)
input logic [7:0] Din, // 8-bit WriteData
output logic [7:0] Dout, // 8-bit ReadData
input logic MEMRb, MEMWb, // Active low memory read/write
output logic INTR, TXRDYb, RXRDYb, // interrupt and ready lines
// Clocks
output logic BAUDOUTb,
input logic RCLK,
output logic BAUDOUTb, // active low baud clock
input logic RCLK, // usually BAUDOUTb tied to RCLK externally
// E1A Driver
input logic SIN, DSRb, DCDb, CTSb, RIb,
output logic SOUT, RTSb, DTRb, OUT1b, OUT2b
);
input logic SIN, DSRb, DCDb, CTSb, RIb, // UART external serial and flow-control inputs
output logic SOUT, RTSb, DTRb, OUT1b, OUT2b // UART external serial and flow-control outputs
);
// signal to watch
// rxparityerr, RXBR[upper 3 bits]
// LSR bits 1 to 4 are based on parity, overrun, and framing errors
// txstate, rxstate
// loop, fifoenabled
// IER, RCR, MCR, LSR, MSR, DLL, DLM, RBR
// transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
// transmit and receive states
typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
// Registers

4
pipelined/src/uncore/uart_apb.sv
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@ -4,9 +4,9 @@
// Written: David_Harris@hmc.edu 21 January 2021
// Modified:
//
// Purpose: Interface to Universial Asynchronous Receiver/ Transmitter with FIFOs
// Purpose: APB Interface to Universial Asynchronous Receiver/ Transmitter with FIFOs
// Emulates interface of Texas Instruments PC165550D
// Compatible with UART in Imperas Virtio model ***
// Compatible with UART in Imperas Virtio model
//
// Documentation: RISC-V System on Chip Design Chapter 15
//