From b302f66baf2b7a12be2723a35a84c0ef357e8924 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 14 Jan 2023 17:07:36 -0800 Subject: [PATCH] uncore cleanup --- pipelined/src/uncore/ram_ahb.sv | 16 +++++----- pipelined/src/uncore/uartPC16550D.sv | 44 ++++++++++++---------------- pipelined/src/uncore/uart_apb.sv | 4 +-- 3 files changed, 28 insertions(+), 36 deletions(-) diff --git a/pipelined/src/uncore/ram_ahb.sv b/pipelined/src/uncore/ram_ahb.sv index 14c8a8a7c..09d1d6a1e 100644 --- a/pipelined/src/uncore/ram_ahb.sv +++ b/pipelined/src/uncore/ram_ahb.sv @@ -42,15 +42,15 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) ( output logic HRESPRam, HREADYRam ); - localparam ADDR_WIDTH = $clog2(RANGE/8); - localparam OFFSET = $clog2(`XLEN/8); + localparam ADDR_WIDTH = $clog2(RANGE/8); + localparam OFFSET = $clog2(`XLEN/8); - logic [`XLEN/8-1:0] ByteMask; - logic [`PA_BITS-1:0] HADDRD, RamAddr; - logic initTrans; - logic memwrite, memwriteD, memread; - logic nextHREADYRam; - logic DelayReady; + logic [`XLEN/8-1:0] ByteMask; + logic [`PA_BITS-1:0] HADDRD, RamAddr; + logic initTrans; + logic memwrite, memwriteD, memread; + logic nextHREADYRam; + logic DelayReady; // a new AHB transactions starts when HTRANS requests a transaction, // the peripheral is selected, and the previous transaction is completing diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index 39f403330..3825c0872 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -38,29 +38,21 @@ module uartPC16550D( // Processor Interface - input logic PCLK, PRESETn, - input logic [2:0] A, - input logic [7:0] Din, - output logic [7:0] Dout, - input logic MEMRb, MEMWb, - output logic INTR, TXRDYb, RXRDYb, + input logic CLK, PRESETn, // UART clock and active low reset + input logic [2:0] A, // address input (8 registers) + input logic [7:0] Din, // 8-bit WriteData + output logic [7:0] Dout, // 8-bit ReadData + input logic MEMRb, MEMWb, // Active low memory read/write + output logic INTR, TXRDYb, RXRDYb, // interrupt and ready lines // Clocks - output logic BAUDOUTb, - input logic RCLK, + output logic BAUDOUTb, // active low baud clock + input logic RCLK, // usually BAUDOUTb tied to RCLK externally // E1A Driver - input logic SIN, DSRb, DCDb, CTSb, RIb, - output logic SOUT, RTSb, DTRb, OUT1b, OUT2b - ); + input logic SIN, DSRb, DCDb, CTSb, RIb, // UART external serial and flow-control inputs + output logic SOUT, RTSb, DTRb, OUT1b, OUT2b // UART external serial and flow-control outputs +); - // signal to watch - // rxparityerr, RXBR[upper 3 bits] - // LSR bits 1 to 4 are based on parity, overrun, and framing errors - // txstate, rxstate - // loop, fifoenabled - // IER, RCR, MCR, LSR, MSR, DLL, DLM, RBR - - - // transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default + // transmit and receive states typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype; // Registers @@ -414,13 +406,13 @@ module uartPC16550D( endcase case({LCR[3], LCR[1:0]}) // parity, data bits // load up start bit (0), 5-8 data bits, 0-1 parity bits, 2 stop bits (only one sometimes used), padding - 3'b000: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], 6'b111111}; // 5 data, no parity - 3'b001: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], 5'b11111}; // 6 data, no parity - 3'b010: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], 4'b1111}; // 7 data, no parity + 3'b000: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], 6'b111111}; // 5 data, no parity + 3'b001: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], 5'b11111}; // 6 data, no parity + 3'b010: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], 4'b1111}; // 7 data, no parity 3'b011: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], nexttxdata[7], 3'b111}; // 8 data, no parity - 3'b100: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], txparity, 5'b11111}; // 5 data, parity - 3'b101: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], txparity, 4'b1111}; // 6 data, parity - 3'b110: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], txparity, 3'b111}; // 7 data, parity + 3'b100: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], txparity, 5'b11111}; // 5 data, parity + 3'b101: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], txparity, 4'b1111}; // 6 data, parity + 3'b110: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], txparity, 3'b111}; // 7 data, parity 3'b111: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], nexttxdata[7], txparity, 2'b11}; // 8 data, parity endcase end diff --git a/pipelined/src/uncore/uart_apb.sv b/pipelined/src/uncore/uart_apb.sv index b7d2b0d50..09df23569 100644 --- a/pipelined/src/uncore/uart_apb.sv +++ b/pipelined/src/uncore/uart_apb.sv @@ -4,9 +4,9 @@ // Written: David_Harris@hmc.edu 21 January 2021 // Modified: // -// Purpose: Interface to Universial Asynchronous Receiver/ Transmitter with FIFOs +// Purpose: APB Interface to Universial Asynchronous Receiver/ Transmitter with FIFOs // Emulates interface of Texas Instruments PC165550D -// Compatible with UART in Imperas Virtio model *** +// Compatible with UART in Imperas Virtio model // // Documentation: RISC-V System on Chip Design Chapter 15 //