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uncore cleanup

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This commit is contained in:
David Harris 2023-01-14 17:07:36 -08:00
parent ae7e7b57ec
commit b302f66baf
3 changed files with 28 additions and 36 deletions
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16
pipelined/src/uncore/ram_ahb.sv
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@ -42,15 +42,15 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
output logic HRESPRam, HREADYRam output logic HRESPRam, HREADYRam
); );
localparam ADDR_WIDTH = $clog2(RANGE/8); localparam ADDR_WIDTH = $clog2(RANGE/8);
localparam OFFSET = $clog2(`XLEN/8); localparam OFFSET = $clog2(`XLEN/8);
logic [`XLEN/8-1:0] ByteMask; logic [`XLEN/8-1:0] ByteMask;
logic [`PA_BITS-1:0] HADDRD, RamAddr; logic [`PA_BITS-1:0] HADDRD, RamAddr;
logic initTrans; logic initTrans;
logic memwrite, memwriteD, memread; logic memwrite, memwriteD, memread;
logic nextHREADYRam; logic nextHREADYRam;
logic DelayReady; logic DelayReady;
// a new AHB transactions starts when HTRANS requests a transaction, // a new AHB transactions starts when HTRANS requests a transaction,
// the peripheral is selected, and the previous transaction is completing // the peripheral is selected, and the previous transaction is completing

44
pipelined/src/uncore/uartPC16550D.sv
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@ -38,29 +38,21 @@
module uartPC16550D( module uartPC16550D(
// Processor Interface // Processor Interface
input logic PCLK, PRESETn, input logic CLK, PRESETn, // UART clock and active low reset
input logic [2:0] A, input logic [2:0] A, // address input (8 registers)
input logic [7:0] Din, input logic [7:0] Din, // 8-bit WriteData
output logic [7:0] Dout, output logic [7:0] Dout, // 8-bit ReadData
input logic MEMRb, MEMWb, input logic MEMRb, MEMWb, // Active low memory read/write
output logic INTR, TXRDYb, RXRDYb, output logic INTR, TXRDYb, RXRDYb, // interrupt and ready lines
// Clocks // Clocks
output logic BAUDOUTb, output logic BAUDOUTb, // active low baud clock
input logic RCLK, input logic RCLK, // usually BAUDOUTb tied to RCLK externally
// E1A Driver // E1A Driver
input logic SIN, DSRb, DCDb, CTSb, RIb, input logic SIN, DSRb, DCDb, CTSb, RIb, // UART external serial and flow-control inputs
output logic SOUT, RTSb, DTRb, OUT1b, OUT2b output logic SOUT, RTSb, DTRb, OUT1b, OUT2b // UART external serial and flow-control outputs
); );
// signal to watch // transmit and receive states
// rxparityerr, RXBR[upper 3 bits]
// LSR bits 1 to 4 are based on parity, overrun, and framing errors
// txstate, rxstate
// loop, fifoenabled
// IER, RCR, MCR, LSR, MSR, DLL, DLM, RBR
// transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype; typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
// Registers // Registers
@ -414,13 +406,13 @@ module uartPC16550D(
endcase endcase
case({LCR[3], LCR[1:0]}) // parity, data bits case({LCR[3], LCR[1:0]}) // parity, data bits
// load up start bit (0), 5-8 data bits, 0-1 parity bits, 2 stop bits (only one sometimes used), padding // load up start bit (0), 5-8 data bits, 0-1 parity bits, 2 stop bits (only one sometimes used), padding
3'b000: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], 6'b111111}; // 5 data, no parity 3'b000: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], 6'b111111}; // 5 data, no parity
3'b001: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], 5'b11111}; // 6 data, no parity 3'b001: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], 5'b11111}; // 6 data, no parity
3'b010: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], 4'b1111}; // 7 data, no parity 3'b010: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], 4'b1111}; // 7 data, no parity
3'b011: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], nexttxdata[7], 3'b111}; // 8 data, no parity 3'b011: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], nexttxdata[7], 3'b111}; // 8 data, no parity
3'b100: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], txparity, 5'b11111}; // 5 data, parity 3'b100: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], txparity, 5'b11111}; // 5 data, parity
3'b101: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], txparity, 4'b1111}; // 6 data, parity 3'b101: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], txparity, 4'b1111}; // 6 data, parity
3'b110: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], txparity, 3'b111}; // 7 data, parity 3'b110: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], txparity, 3'b111}; // 7 data, parity
3'b111: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], nexttxdata[7], txparity, 2'b11}; // 8 data, parity 3'b111: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], nexttxdata[7], txparity, 2'b11}; // 8 data, parity
endcase endcase
end end

4
pipelined/src/uncore/uart_apb.sv
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@ -4,9 +4,9 @@
// Written: David_Harris@hmc.edu 21 January 2021 // Written: David_Harris@hmc.edu 21 January 2021
// Modified: // Modified:
// //
// Purpose: Interface to Universial Asynchronous Receiver/ Transmitter with FIFOs // Purpose: APB Interface to Universial Asynchronous Receiver/ Transmitter with FIFOs
// Emulates interface of Texas Instruments PC165550D // Emulates interface of Texas Instruments PC165550D
// Compatible with UART in Imperas Virtio model *** // Compatible with UART in Imperas Virtio model
// //
// Documentation: RISC-V System on Chip Design Chapter 15 // Documentation: RISC-V System on Chip Design Chapter 15
// //