uncore cleanup

pipelined/src/uncore/uartPC16550D.sv

@@ -38,29 +38,21 @@
 
 module uartPC16550D(
 	// Processor Interface
-	input logic 	   PCLK, PRESETn,
+	input  logic 	      CLK, PRESETn,                   // UART clock and active low reset
-	input logic [2:0]  A,
+	input  logic [2:0]  A,                              // address input (8 registers)
-	input logic [7:0]  Din,
+	input  logic [7:0]  Din,                            // 8-bit WriteData
-	output logic [7:0] Dout,
+	output logic [7:0]  Dout,                           // 8-bit ReadData
-	input logic 	   MEMRb, MEMWb, 
+	input  logic 	      MEMRb, MEMWb,                   // Active low memory read/write
-	output logic 	   INTR, TXRDYb, RXRDYb,
+	output logic 	      INTR, TXRDYb, RXRDYb,           // interrupt and ready lines
 	// Clocks
-	output logic 	   BAUDOUTb,
+	output logic 	      BAUDOUTb,                       // active low baud clock
-	input logic 	   RCLK,
+	input logic 	      RCLK,                           // usually BAUDOUTb tied to RCLK externally
 	// E1A Driver
-	input logic 	   SIN, DSRb, DCDb, CTSb, RIb,
+	input  logic 	      SIN, DSRb, DCDb, CTSb, RIb,     // UART external serial and flow-control inputs
-	output logic 	   SOUT, RTSb, DTRb, OUT1b, OUT2b
+	output logic 	      SOUT, RTSb, DTRb, OUT1b, OUT2b  // UART external serial and flow-control outputs
 );
 
-  // signal to watch
+  // transmit and receive states 
-  // rxparityerr, RXBR[upper 3 bits]
-  // LSR bits 1 to 4 are based on parity, overrun, and framing errors
-  // txstate, rxstate
-  // loop, fifoenabled
-  // IER, RCR, MCR, LSR, MSR, DLL, DLM, RBR
-  
-
-  // transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
   typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
 
   // Registers

pipelined/src/uncore/uart_apb.sv

@@ -4,9 +4,9 @@
 // Written: David_Harris@hmc.edu 21 January 2021
 // Modified: 
 //
-// Purpose: Interface to Universial Asynchronous Receiver/ Transmitter with FIFOs
+// Purpose: APB Interface to Universial Asynchronous Receiver/ Transmitter with FIFOs
 //          Emulates interface of Texas Instruments PC165550D
-//          Compatible with UART in Imperas Virtio model ***
+//          Compatible with UART in Imperas Virtio model
 // 
 // Documentation: RISC-V System on Chip Design Chapter 15
 //