diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S index 2c9a698dc..0c4477619 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S @@ -52,9 +52,9 @@ GOTO_U_MODE // Causes S mode ecall GOTO_S_MODE // Causes U mode ecall +// some interrupts excluded becaus writing MIP is illegal from S mode jal cause_s_soft_interrupt jal cause_m_soft_interrupt -//jal cause_s_time_interrupt // *** S time interrupts cannot come from S mode as of 4/19/22. jal cause_m_time_interrupt li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. // since interrupts are not always enabled, @@ -84,13 +84,10 @@ jal cause_store_acc GOTO_U_MODE // Causes S mode ecall GOTO_S_MODE // Causes U mode ecall -jal cause_s_soft_interrupt // *** M mode Interrupts cannot be delegated in this implementation -//jal cause_m_soft_interrupt -//jal cause_s_time_interrupt -//jal cause_m_time_interrupt +// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests +jal cause_s_soft_interrupt li a3, 0x40 jal cause_s_ext_interrupt_GPIO -//jal cause_m_ext_interrupt END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S index 447858157..326f53625 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S @@ -50,9 +50,8 @@ jal cause_store_addr_misaligned jal cause_store_acc jal cause_ecall -//jal cause_s_soft_interrupt // *** writing SIP from u mode is illegal +// some interrupts excluded becaus writing SIP/MIP is illegal from U mode jal cause_m_soft_interrupt -//jal cause_s_time_interrupt // *** S time interrupts cannot come from U mode as of 4/19/22. jal cause_m_time_interrupt li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. // since interrupts are not always enabled, @@ -81,15 +80,9 @@ jal cause_store_addr_misaligned jal cause_store_acc jal cause_ecall -//jal cause_s_soft_interrupt // *** S Soft interrupts cannot be caused from u mode since writing SIP is illegal -// *** M mode Interrupts cannot be delegated in this implementation -//jal cause_m_soft_interrupt -//jal cause_s_time_interrupt -//jal cause_m_time_interrupt +// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests li a3, 0x40 jal cause_s_ext_interrupt_GPIO -//jal cause_m_ext_interrupt - END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S index 281721ea8..8e72a6f1b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S @@ -52,9 +52,9 @@ GOTO_U_MODE // Causes S mode ecall GOTO_S_MODE // Causes U mode ecall +// some interrupts excluded becaus writing MIP is illegal from S mode jal cause_s_soft_interrupt jal cause_m_soft_interrupt -//jal cause_s_time_interrupt // *** S time interrupts cannot come from S mode as of 4/19/22. jal cause_m_time_interrupt li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. // since interrupts are not always enabled, @@ -84,14 +84,10 @@ jal cause_store_acc GOTO_U_MODE // Causes S mode ecall GOTO_S_MODE // Causes U mode ecall -jal cause_s_soft_interrupt // *** M mode Interrupts cannot be delegated in this implementation -//jal cause_m_soft_interrupt -//jal cause_s_time_interrupt -//jal cause_m_time_interrupt +// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests +jal cause_s_soft_interrupt li a3, 0x40 jal cause_s_ext_interrupt_GPIO -//jal cause_m_ext_interrupt - END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S index 6b90538da..104e03f36 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S @@ -50,9 +50,8 @@ jal cause_store_addr_misaligned jal cause_store_acc jal cause_ecall -//jal cause_s_soft_interrupt // *** writing SIP from u mode is illegal +// some interrupts excluded becaus writing SIP/MIP is illegal from U mode jal cause_m_soft_interrupt -//jal cause_s_time_interrupt // *** S time interrupts cannot come from U mode as of 4/19/22. jal cause_m_time_interrupt li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. // since interrupts are not always enabled, @@ -81,15 +80,9 @@ jal cause_store_addr_misaligned jal cause_store_acc jal cause_ecall -//jal cause_s_soft_interrupt // *** S Soft interrupts cannot be caused from u mode since writing SIP is illegal -// *** M mode Interrupts cannot be delegated in this implementation -//jal cause_m_soft_interrupt -//jal cause_s_time_interrupt -//jal cause_m_time_interrupt +// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests li a3, 0x40 jal cause_s_ext_interrupt_GPIO -//jal cause_m_ext_interrupt - END_TESTS