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fix regression

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bbracker 2021-09-15 17:30:59 -04:00
parent f94a13e242
commit b1be8f4858
2 changed files with 16 additions and 14 deletions
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4
wally-pipelined/regression/regression-wally.py
View File

@ -31,7 +31,7 @@ configs = [
TestCase( TestCase(
name="buildroot", name="buildroot",
cmd="vsim -do wally-buildroot-batch.do -c > {}", cmd="vsim -do wally-buildroot-batch.do -c > {}",
grepstr="loaded 6000 instructions" grepstr="8900000 instructions"
), ),
TestCase( TestCase(
name="arch64", name="arch64",
@ -81,7 +81,7 @@ def main():
"""Run the tests and count the failures""" """Run the tests and count the failures"""
# Scale the number of concurrent processes to the number of test cases, but # Scale the number of concurrent processes to the number of test cases, but
# max out at 12 concurrent processes to not overwhelm the system # max out at 12 concurrent processes to not overwhelm the system
TIMEOUT_DUR = 600 # seconds TIMEOUT_DUR = 1800 # seconds
try: try:
os.mkdir("regression_logs") os.mkdir("regression_logs")
except: except:

26
wally-pipelined/testbench/testbench-linux.sv
View File

@ -363,38 +363,40 @@ module testbench();
InstrCountW += 1; InstrCountW += 1;
// turn on waves at certain point // turn on waves at certain point
if (InstrCountW == waveOnICount) $stop; if (InstrCountW == waveOnICount) $stop;
// print progress message
if (InstrCountW % 'd100000 == 0) $display("Reached %d instructions", InstrCountW);
// check PCW // check PCW
fault = 0; fault = 0;
if(PCW != ExpectedPCW) begin if(PCW != ExpectedPCW) begin
$display("PCW: %016x does not equal ExpectedPCW: %016x", PCW, ExpectedPCW); $display("PCW: %016x does not equal ExpectedPCW: %016x", PCW, ExpectedPCW);
fault = 1; fault = 1;
end end
// check instruction value // check instruction value
if(dut.hart.ifu.InstrW != ExpectedInstrW) begin if(dut.hart.ifu.InstrW != ExpectedInstrW) begin
$display("InstrW: %x does not equal ExpectedInstrW: %x", dut.hart.ifu.InstrW, ExpectedInstrW); $display("InstrW: %x does not equal ExpectedInstrW: %x", dut.hart.ifu.InstrW, ExpectedInstrW);
fault = 1; fault = 1;
end end
// check the number of instructions // check the number of instructions
if(dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW != InstrCountW) begin if(dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW != InstrCountW) begin
$display("%t, Number of instruction Retired = %d does not equal number of instructions in trace = %d", $time, dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW, InstrCountW); $display("%t, Number of instruction Retired = %d does not equal number of instructions in trace = %d", $time, dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW, InstrCountW);
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
#2; // delay 2 ns. #2; // delay 2 ns.
if(`DEBUG_TRACE > 2) begin if(`DEBUG_TRACE > 2) begin
$display("Reg Write Address: %02d ? expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW); $display("Reg Write Address: %02d ? expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
$display("RF[%02d]: %016x ? expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); $display("RF[%02d]: %016x ? expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
end end
if (RegWriteW == "GPR") begin if (RegWriteW == "GPR") begin
if (dut.hart.ieu.dp.regf.a3 != ExpectedRegAdrW) begin if (dut.hart.ieu.dp.regf.a3 != ExpectedRegAdrW) begin
$display("Reg Write Address: %02d does not equal expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW); $display("Reg Write Address: %02d does not equal expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
fault = 1; fault = 1;
end end
if (dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW] != ExpectedRegValueW) begin if (dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW] != ExpectedRegValueW) begin
$display("RF[%02d]: %016x does not equal expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); $display("RF[%02d]: %016x does not equal expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);