From b1be8f4858afc474be0bf0df8b222f4d428c3922 Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Wed, 15 Sep 2021 17:30:59 -0400
Subject: [PATCH] fix regression

---
 .../regression/regression-wally.py            |  4 +--
 wally-pipelined/testbench/testbench-linux.sv  | 26 ++++++++++---------
 2 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py
index 4d7baf8e5..c0b86f494 100755
--- a/wally-pipelined/regression/regression-wally.py
+++ b/wally-pipelined/regression/regression-wally.py
@@ -31,7 +31,7 @@ configs = [
     TestCase(
         name="buildroot",
         cmd="vsim -do wally-buildroot-batch.do -c > {}",
-        grepstr="loaded 6000 instructions"
+        grepstr="8900000 instructions"
     ),
     TestCase(
         name="arch64",
@@ -81,7 +81,7 @@ def main():
     """Run the tests and count the failures"""
     # Scale the number of concurrent processes to the number of test cases, but
     # max out at 12 concurrent processes to not overwhelm the system
-    TIMEOUT_DUR = 600 # seconds
+    TIMEOUT_DUR = 1800 # seconds
     try:
         os.mkdir("regression_logs")
     except:
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index 40e0e75c4..64bd24e70 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -363,38 +363,40 @@ module testbench();
       InstrCountW += 1;
       // turn on waves at certain point
       if (InstrCountW == waveOnICount) $stop;
+      // print progress message
+      if (InstrCountW % 'd100000 == 0) $display("Reached %d instructions", InstrCountW);
       // check PCW
       fault = 0;
       if(PCW != ExpectedPCW) begin
-    $display("PCW: %016x does not equal ExpectedPCW: %016x", PCW, ExpectedPCW);
-    fault = 1;
+        $display("PCW: %016x does not equal ExpectedPCW: %016x", PCW, ExpectedPCW);
+        fault = 1;
       end
 
       // check instruction value
       if(dut.hart.ifu.InstrW != ExpectedInstrW) begin
-    $display("InstrW: %x does not equal ExpectedInstrW: %x", dut.hart.ifu.InstrW, ExpectedInstrW);
-    fault = 1;
+        $display("InstrW: %x does not equal ExpectedInstrW: %x", dut.hart.ifu.InstrW, ExpectedInstrW);
+        fault = 1;
       end
 
       // check the number of instructions
       if(dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW != InstrCountW) begin
-    $display("%t, Number of instruction Retired = %d does not equal number of instructions in trace = %d", $time, dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW, InstrCountW);
-    if(!`DontHaltOnCSRMisMatch) fault = 1;
+        $display("%t, Number of instruction Retired = %d does not equal number of instructions in trace = %d", $time, dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW, InstrCountW);
+        if(!`DontHaltOnCSRMisMatch) fault = 1;
       end
       
       #2; // delay 2 ns.
 
       
       if(`DEBUG_TRACE > 2) begin
-    $display("Reg Write Address: %02d ? expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
-    $display("RF[%02d]: %016x ? expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
+        $display("Reg Write Address: %02d ? expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
+        $display("RF[%02d]: %016x ? expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
       end
 
       if (RegWriteW == "GPR") begin
-    if (dut.hart.ieu.dp.regf.a3 != ExpectedRegAdrW) begin
-      $display("Reg Write Address: %02d does not equal expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
-      fault = 1;
-    end
+        if (dut.hart.ieu.dp.regf.a3 != ExpectedRegAdrW) begin
+          $display("Reg Write Address: %02d does not equal expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
+          fault = 1;
+        end
     
     if (dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW] != ExpectedRegValueW) begin
       $display("RF[%02d]: %016x does not equal expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);