Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

fix operator for ir and rad

Browse Source
This commit is contained in:
James Stine 2024-06-04 10:59:04 -05:00
parent bdbd310bb4
commit ae4900698e
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/debug/ir.sv
View File

@ -49,12 +49,12 @@ module ir (
// Shift register
always @(posedge clockIR) begin
shift_reg[0] <= shift_reg[1] || captureIR;
shift_reg[0] <= shift_reg[1] | captureIR;
end
genvar i;
for (i = INST_REG_WIDTH; i > 1; i = i - 1) begin
always @(posedge clockIR) begin
shift_reg[i-1] <= shift_reg[i] && ~captureIR;
shift_reg[i-1] <= shift_reg[i] & ~captureIR;
end
end

4
src/debug/rad.sv
View File

@ -135,8 +135,8 @@ module rad import cvw::*; #(parameter cvw_t P) (
assign ARMask[31:0] = Mask[31:0];
if (P.XLEN >= 64)
assign ARMask[63:32] = (AarSize == 3'b011 || AarSize == 3'b100) ? Mask[63:32] : '0;
assign ARMask[63:32] = (AarSize == 3'b011 | AarSize == 3'b100) ? Mask[63:32] : '0;
if (P.XLEN == 128)
assign ARMask[127:64] = (AarSize == 3'b100) ? Mask[127:64] : '0;
endmodule
endmodule