diff --git a/src/debug/ir.sv b/src/debug/ir.sv
index 767430884..dd99c7cc1 100644
--- a/src/debug/ir.sv
+++ b/src/debug/ir.sv
@@ -49,12 +49,12 @@ module ir (
 
   // Shift register
   always @(posedge clockIR) begin
-    shift_reg[0] <= shift_reg[1] || captureIR;
+    shift_reg[0] <= shift_reg[1] | captureIR;
   end
   genvar i;
   for (i = INST_REG_WIDTH; i > 1; i = i - 1) begin
     always @(posedge clockIR) begin
-      shift_reg[i-1] <= shift_reg[i] && ~captureIR;
+      shift_reg[i-1] <= shift_reg[i] & ~captureIR;
     end
   end
 
diff --git a/src/debug/rad.sv b/src/debug/rad.sv
index 565316ea1..a1e8ec148 100644
--- a/src/debug/rad.sv
+++ b/src/debug/rad.sv
@@ -135,8 +135,8 @@ module rad import cvw::*; #(parameter cvw_t P) (
 
   assign ARMask[31:0] = Mask[31:0];
   if (P.XLEN >= 64)
-    assign ARMask[63:32] = (AarSize == 3'b011 || AarSize == 3'b100) ? Mask[63:32] : '0;
+    assign ARMask[63:32] = (AarSize == 3'b011 | AarSize == 3'b100) ? Mask[63:32] : '0;
   if (P.XLEN == 128)
     assign ARMask[127:64] = (AarSize == 3'b100) ? Mask[127:64] : '0;
 
-endmodule
\ No newline at end of file
+endmodule