Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Update rom_ahb.sv

Browse Source 
Program clean up
This commit is contained in:
Harshini Srinath 2023-06-15 10:13:15 -07:00 committed by GitHub
parent 97917c2a44
commit ae165b35f9
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 9 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
src/uncore/rom_ahb.sv
View File

@ -28,24 +28,23 @@
module rom_ahb import cvw::*; #(parameter cvw_t P,
parameter BASE=0, RANGE = 65535) (
input logic HCLK, HRESETn,
input logic HSELRom,
input logic [P.PA_BITS-1:0] HADDR,
input logic HREADY,
input logic [1:0] HTRANS,
output logic [P.XLEN-1:0] HREADRom,
output logic HRESPRom, HREADYRom
input logic HCLK, HRESETn,
input logic HSELRom,
input logic [P.PA_BITS-1:0] HADDR,
input logic HREADY,
input logic [1:0] HTRANS,
output logic [P.XLEN-1:0] HREADRom,
output logic HRESPRom, HREADYRom
);
localparam ADDR_WIDTH = $clog2(RANGE/8);
localparam OFFSET = $clog2(P.XLEN/8);
localparam OFFSET = $clog2(P.XLEN/8);
// Never stalls
assign HREADYRom = 1'b1;
assign HRESPRom = 0; // OK
assign HRESPRom = 0; // OK
// single-ported ROM
rom1p1r #(ADDR_WIDTH, P.XLEN, P.FPGA)
memory(.clk(HCLK), .ce(1'b1), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));
endmodule