From ae165b35f9561d9eff0233fd417e63714c427720 Mon Sep 17 00:00:00 2001
From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com>
Date: Thu, 15 Jun 2023 10:13:15 -0700
Subject: [PATCH] Update rom_ahb.sv

Program clean up
---
 src/uncore/rom_ahb.sv | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv
index abb75277f..0c09191be 100644
--- a/src/uncore/rom_ahb.sv
+++ b/src/uncore/rom_ahb.sv
@@ -28,24 +28,23 @@
 
 module rom_ahb import cvw::*;  #(parameter cvw_t P, 
                                  parameter BASE=0, RANGE = 65535) (
-  input  logic             HCLK, HRESETn, 
-  input  logic             HSELRom,
-  input  logic [P.PA_BITS-1:0]  HADDR,
-  input  logic             HREADY,
-  input  logic [1:0]       HTRANS,
-  output logic [P.XLEN-1:0] HREADRom,
-  output logic             HRESPRom, HREADYRom
+  input  logic                 HCLK, HRESETn, 
+  input  logic                 HSELRom,
+  input  logic [P.PA_BITS-1:0] HADDR,
+  input  logic                 HREADY,
+  input  logic [1:0]           HTRANS,
+  output logic [P.XLEN-1:0]    HREADRom,
+  output logic                 HRESPRom, HREADYRom
 );
 
   localparam ADDR_WIDTH = $clog2(RANGE/8);
-  localparam OFFSET = $clog2(P.XLEN/8);   
+  localparam OFFSET     = $clog2(P.XLEN/8);   
  
   // Never stalls
   assign HREADYRom = 1'b1;
-  assign HRESPRom = 0; // OK
+  assign HRESPRom  = 0; // OK
 
   // single-ported ROM
   rom1p1r #(ADDR_WIDTH, P.XLEN, P.FPGA)
     memory(.clk(HCLK), .ce(1'b1), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));  
 endmodule
-