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Update rom_ahb.sv

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Program clean up
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Harshini Srinath 2023-06-15 10:13:15 -07:00 committed by GitHub
parent 97917c2a44
commit ae165b35f9
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1 changed files with 9 additions and 10 deletions
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src/uncore/rom_ahb.sv
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@ -28,24 +28,23 @@
module rom_ahb import cvw::*; #(parameter cvw_t P, module rom_ahb import cvw::*; #(parameter cvw_t P,
parameter BASE=0, RANGE = 65535) ( parameter BASE=0, RANGE = 65535) (
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
input logic HSELRom, input logic HSELRom,
input logic [P.PA_BITS-1:0] HADDR, input logic [P.PA_BITS-1:0] HADDR,
input logic HREADY, input logic HREADY,
input logic [1:0] HTRANS, input logic [1:0] HTRANS,
output logic [P.XLEN-1:0] HREADRom, output logic [P.XLEN-1:0] HREADRom,
output logic HRESPRom, HREADYRom output logic HRESPRom, HREADYRom
); );
localparam ADDR_WIDTH = $clog2(RANGE/8); localparam ADDR_WIDTH = $clog2(RANGE/8);
localparam OFFSET = $clog2(P.XLEN/8); localparam OFFSET = $clog2(P.XLEN/8);
// Never stalls // Never stalls
assign HREADYRom = 1'b1; assign HREADYRom = 1'b1;
assign HRESPRom = 0; // OK assign HRESPRom = 0; // OK
// single-ported ROM // single-ported ROM
rom1p1r #(ADDR_WIDTH, P.XLEN, P.FPGA) rom1p1r #(ADDR_WIDTH, P.XLEN, P.FPGA)
memory(.clk(HCLK), .ce(1'b1), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom)); memory(.clk(HCLK), .ce(1'b1), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));
endmodule endmodule