From adfeb29b7730078d0524dc702fd5fa99fc1cecce Mon Sep 17 00:00:00 2001
From: Noah Boorstin <nboorstin@hmc.edu>
Date: Fri, 22 Jan 2021 15:11:55 -0500
Subject: [PATCH] change regfile to not hold state of x0

---
 wally-pipelined/src/regfile.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/wally-pipelined/src/regfile.sv b/wally-pipelined/src/regfile.sv
index a92497d01..78238a823 100644
--- a/wally-pipelined/src/regfile.sv
+++ b/wally-pipelined/src/regfile.sv
@@ -32,7 +32,7 @@ module regfile #(parameter XLEN=32) (
   input  logic [XLEN-1:0] wd3, 
   output logic [XLEN-1:0] rd1, rd2);
 
-  logic [XLEN-1:0] rf[31:0];
+  logic [XLEN-1:0] rf[31:1];
   integer i;
 
   // three ported register file
@@ -45,7 +45,7 @@ module regfile #(parameter XLEN=32) (
     
   always_ff @(negedge clk or posedge reset)
     if (reset) for(i=0; i<32; i++) rf[i] <= 0;
-    else if (we3) rf[a3] <= wd3;	
+    else if (we3 & (a3 != 0)) rf[a3] <= wd3;	
 
   assign #2 rd1 = (a1 != 0) ? rf[a1] : 0;
   assign #2 rd2 = (a2 != 0) ? rf[a2] : 0;