diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index f2f16b51e..97aec3868 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -71,7 +71,7 @@ module bpred ( logic [1:0] BPDirPredF; - logic [`XLEN-1:0] BTAF, RASPCF; + logic [`XLEN-1:0] BPBTAF, RASPCF; logic BPPCWrongE; logic IClassWrongE; logic BPDirPredWrongE; @@ -85,7 +85,7 @@ module bpred ( logic BTBTargetWrongE; logic RASTargetWrongE; - logic [`XLEN-1:0] BTAD; + logic [`XLEN-1:0] BPBTAD; logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF; logic BPBranchF, BPJumpF, BPReturnF, BPCallF; @@ -95,7 +95,7 @@ module bpred ( logic BranchM, JumpM, ReturnM, CallM; logic BranchW, JumpW, ReturnW, CallW; logic BPReturnWrongD; - logic [`XLEN-1:0] BTAE; + logic [`XLEN-1:0] BPBTAE; @@ -150,7 +150,7 @@ module bpred ( btb #(`BTB_SIZE) TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, - .BTAF, .BTAD, .BTAE, + .BPBTAF, .BPBTAD, .BPBTAE, .BTBIClassF({BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF}), .IClassWrongM, .IClassWrongE, .IEUAdrE, .IEUAdrM, @@ -181,7 +181,7 @@ module bpred ( // Output the predicted PC or corrected PC on miss-predict. assign BPPCSrcF = (BPBranchF & BPDirPredF[1]) | BPJumpF; - mux2 #(`XLEN) pcmuxbp(BTAF, RASPCF, BPReturnF, BPPCF); + mux2 #(`XLEN) pcmuxbp(BPBTAF, RASPCF, BPReturnF, BPPCF); // Selects the BP or PC+2/4. mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPCF, BPPCSrcF, PC0NextF); // If the prediction is wrong select the correct address. @@ -196,7 +196,7 @@ module bpred ( if(`ZICOUNTERS_SUPPORTED) begin logic [`XLEN-1:0] RASPCD, RASPCE; - logic BTBPredPCWrongE, RASPredPCWrongE; + logic BTAWrongE, RASPredPCWrongE; // performance counters // 1. class (class wrong / minstret) (IClassWrongM / csr) // Correct now // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) @@ -207,14 +207,14 @@ module bpred ( // could be wrong or the fall through address selected for branch predict not taken. // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // both without the above inaccuracies. - // **** use BTAWrongM from BTB. - assign BTBPredPCWrongE = (BTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE; + // **** use BPBTAWrongM from BTB. + assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE; assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE; flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM, - {BPDirPredWrongE, BTBPredPCWrongE, RASPredPCWrongE}, + {BPDirPredWrongE, BTAWrongE, RASPredPCWrongE}, {BPDirPredWrongM, BTAWrongM, RASPredPCWrongM}); end else begin diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index b14399704..ab11b48be 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -35,9 +35,9 @@ module btb #(parameter Depth = 10 ) ( input logic reset, input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,// PC at various stages - output logic [`XLEN-1:0] BTAF, // BTB's guess at PC - output logic [`XLEN-1:0] BTAD, - output logic [`XLEN-1:0] BTAE, + output logic [`XLEN-1:0] BPBTAF, // BTB's guess at PC + output logic [`XLEN-1:0] BPBTAD, + output logic [`XLEN-1:0] BPBTAE, output logic [3:0] BTBIClassF, // BTB's guess at instruction class // update input logic IClassWrongM, // BTB's instruction class guess was wrong @@ -57,8 +57,8 @@ module btb #(parameter Depth = 10 ) ( logic [`XLEN+3:0] TableBTBPredF; logic [`XLEN-1:0] IEUAdrW; logic [`XLEN-1:0] PCW; - logic BTBWrongE, BTAWrongE; - logic BTBWrongM, BTAWrongM; + logic BTBWrongE, BPBTAWrongE; + logic BTBWrongM, BPBTAWrongM; // hashing function for indexing the PC @@ -84,12 +84,12 @@ module btb #(parameter Depth = 10 ) ( assign MatchW = PCFIndex == PCWIndex; assign MatchX = MatchD | MatchE | MatchM | MatchW; - assign ForwardBTBPredictionF = MatchD ? {InstrClassD, BTAD} : + assign ForwardBTBPredictionF = MatchD ? {InstrClassD, BPBTAD} : MatchE ? {InstrClassE, IEUAdrE} : MatchM ? {InstrClassM, IEUAdrM} : {InstrClassW, IEUAdrW} ; - assign {BTBIClassF, BTAF} = MatchX ? ForwardBTBPredictionF : {TableBTBPredF}; + assign {BTBIClassF, BPBTAF} = MatchX ? ForwardBTBPredictionF : {TableBTBPredF}; // An optimization may be using a PC relative address. @@ -97,16 +97,16 @@ module btb #(parameter Depth = 10 ) ( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF), .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1)); - flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, BTAF, BTAD); + flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, BPBTAF, BPBTAD); - // BTAE is not strickly necessary. However it is used by two parts of wally. + // BPBTAE is not strickly necessary. However it is used by two parts of wally. // 1. It gates updates to the BTB when the prediction does not change. This save power. - // 2. BTAWrongE is used by the performance counters to track when the BTB's BTA or instruction class is wrong. - flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BTAD, BTAE); - assign BTAWrongE = (BTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]); + // 2. BPBTAWrongE is used by the performance counters to track when the BTB's BPBTA or instruction class is wrong. + flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BPBTAD, BPBTAE); + assign BPBTAWrongE = (BPBTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]); - flopenrc #(1) BTAWrongMReg(clk, reset, FlushM, ~StallM, BTAWrongE, BTAWrongM); - assign BTBWrongM = BTAWrongM | IClassWrongM; + flopenrc #(1) BPBTAWrongMReg(clk, reset, FlushM, ~StallM, BPBTAWrongE, BPBTAWrongM); + assign BTBWrongM = BPBTAWrongM | IClassWrongM; flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); flopenr #(`XLEN) IEUAdrWReg(clk, reset, ~StallW, IEUAdrM, IEUAdrW);