mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Incorporated new AMO tests from riscv-arch-test
This commit is contained in:
David Harris
parent
6245748ed7
commit
ac4216b43d
@ -85,7 +85,7 @@ for test in tests64i:
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configs.append(tc)
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configs.append(tc)
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tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
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tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
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tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"]
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tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"]
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for test in tests32gc:
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for test in tests32gc:
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tc = TestCase(
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tc = TestCase(
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name=test,
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name=test,
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@ -133,7 +133,7 @@ for test in ahbTests:
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configs.append(tc)
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configs.append(tc)
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tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
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tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
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"arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
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"arch64priv", "arch64c", "arch64m", "arch64a", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
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if (coverage): # delete all but 64gc tests when running coverage
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if (coverage): # delete all but 64gc tests when running coverage
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configs = []
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configs = []
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tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
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tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
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@ -52,6 +52,8 @@ tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
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"arch64zi", "wally64a", "wally64periph", "wally64priv",
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"arch64zi", "wally64a", "wally64periph", "wally64priv",
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"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
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"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
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"imperas64f", "imperas64d", "imperas64c", "imperas64i"]
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"imperas64f", "imperas64d", "imperas64c", "imperas64i"]
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# arch64i is the most interesting case. Uncomment line below to run just that case
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tests64gc = ["arch64i"]
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cachetypes = ["ICache", "DCache"]
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cachetypes = ["ICache", "DCache"]
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simdir = os.path.expanduser("~/cvw/sim")
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simdir = os.path.expanduser("~/cvw/sim")
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@ -38,8 +38,8 @@ module testbench;
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parameter TEST="none";
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parameter TEST="none";
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parameter PrintHPMCounters=1;
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parameter PrintHPMCounters=1;
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parameter BPRED_LOGGER=0;
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parameter BPRED_LOGGER=0;
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parameter I_CACHE_ADDR_LOGGER=0;
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parameter I_CACHE_ADDR_LOGGER=1;
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parameter D_CACHE_ADDR_LOGGER=0;
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parameter D_CACHE_ADDR_LOGGER=1;
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`include "parameter-defs.vh"
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`include "parameter-defs.vh"
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@ -98,6 +98,7 @@ module testbench;
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if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
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if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
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else tests = {arch64c};
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else tests = {arch64c};
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"arch64m": if (P.M_SUPPORTED) tests = arch64m;
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"arch64m": if (P.M_SUPPORTED) tests = arch64m;
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"arch64a": if (P.A_SUPPORTED) tests = arch64a;
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"arch64f": if (P.F_SUPPORTED) tests = arch64f;
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"arch64f": if (P.F_SUPPORTED) tests = arch64f;
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"arch64d": if (P.D_SUPPORTED) tests = arch64d;
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"arch64d": if (P.D_SUPPORTED) tests = arch64d;
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"arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma;
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"arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma;
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@ -131,6 +132,7 @@ module testbench;
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if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
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if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
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else tests = {arch32c};
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else tests = {arch32c};
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"arch32m": if (P.M_SUPPORTED) tests = arch32m;
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"arch32m": if (P.M_SUPPORTED) tests = arch32m;
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"arch32a": if (P.A_SUPPORTED) tests = arch32a;
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"arch32f": if (P.F_SUPPORTED) tests = arch32f;
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"arch32f": if (P.F_SUPPORTED) tests = arch32f;
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"arch32d": if (P.D_SUPPORTED) tests = arch32d;
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"arch32d": if (P.D_SUPPORTED) tests = arch32d;
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"arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma;
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"arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma;
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@ -864,13 +864,11 @@ string imperas32f[] = '{
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string wally64a[] = '{
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string wally64a[] = '{
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`WALLYTEST,
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`WALLYTEST,
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"rv64i_m/privilege/src/WALLY-amo-01.S",
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"rv64i_m/privilege/src/WALLY-lrsc-01.S"
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"rv64i_m/privilege/src/WALLY-lrsc-01.S"
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};
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};
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string wally32a[] = '{
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string wally32a[] = '{
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`WALLYTEST,
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`WALLYTEST,
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"rv32i_m/privilege/src/WALLY-amo-01.S",
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"rv32i_m/privilege/src/WALLY-lrsc-01.S"
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"rv32i_m/privilege/src/WALLY-lrsc-01.S"
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};
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};
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@ -902,6 +900,20 @@ string imperas32f[] = '{
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"rv64i_m/Zifencei/src/Fencei.S"
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"rv64i_m/Zifencei/src/Fencei.S"
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};
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};
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string arch32a[] = '{
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`RISCVARCHTEST,
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"rv32i_m/A/src/amoadd.w-01.S",
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"rv32i_m/A/src/amoand.w-01.S",
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"rv32i_m/A/src/amomax.w-01.S",
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"rv32i_m/A/src/amomaxu.w-01.S",
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"rv32i_m/A/src/amomin.w-01.S",
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"rv32i_m/A/src/amominu.w-01.S",
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"rv32i_m/A/src/amoor.w-01.S",
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"rv32i_m/A/src/amoswap.w-01.S",
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"rv32i_m/A/src/amoxor.w-01.S"
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};
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string arch32zi[] = '{
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string arch32zi[] = '{
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`RISCVARCHTEST,
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`RISCVARCHTEST,
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"rv32i_m/Zifencei/src/Fencei.S"
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"rv32i_m/Zifencei/src/Fencei.S"
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@ -972,6 +984,28 @@ string imperas32f[] = '{
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"rv64i_m/M/src/remw-01.S"
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"rv64i_m/M/src/remw-01.S"
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};
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};
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string arch64a[] = '{
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`RISCVARCHTEST,
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"rv64i_m/A/src/amoadd.w-01.S",
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"rv64i_m/A/src/amoand.w-01.S",
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"rv64i_m/A/src/amomax.w-01.S",
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"rv64i_m/A/src/amomaxu.w-01.S",
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"rv64i_m/A/src/amomin.w-01.S",
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"rv64i_m/A/src/amominu.w-01.S",
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"rv64i_m/A/src/amoor.w-01.S",
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"rv64i_m/A/src/amoswap.w-01.S",
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"rv64i_m/A/src/amoxor.w-01.S",
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"rv64i_m/A/src/amoadd.d-01.S",
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"rv64i_m/A/src/amoand.d-01.S",
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"rv64i_m/A/src/amomax.d-01.S",
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"rv64i_m/A/src/amomaxu.d-01.S",
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"rv64i_m/A/src/amomin.d-01.S",
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"rv64i_m/A/src/amominu.d-01.S",
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"rv64i_m/A/src/amoor.d-01.S",
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"rv64i_m/A/src/amoswap.d-01.S",
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"rv64i_m/A/src/amoxor.d-01.S"
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};
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string arch64c[] = '{
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string arch64c[] = '{
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`RISCVARCHTEST,
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`RISCVARCHTEST,
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"rv64i_m/C/src/cadd-01.S",
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"rv64i_m/C/src/cadd-01.S",
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@ -1936,6 +1970,7 @@ string arch64zbs[] = '{
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string wally64priv[] = '{
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string wally64priv[] = '{
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`WALLYTEST,
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`WALLYTEST,
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"rv64i_m/privilege/src/WALLY-minfo-01.S",
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"rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
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"rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
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"rv64i_m/privilege/src/WALLY-cboz-01.S",
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"rv64i_m/privilege/src/WALLY-cboz-01.S",
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"rv64i_m/privilege/src/WALLY-cbom-01.S",
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"rv64i_m/privilege/src/WALLY-cbom-01.S",
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@ -29,19 +29,18 @@
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rv32i_sc_tests = \
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rv32i_sc_tests = \
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WALLY-mmu-sv32 \
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WALLY-mmu-sv32 \
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WALLY-pmp \
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WALLY-pm-01 \
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WALLY-csr-permission-s-01 \
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WALLY-csr-permission-s-01 \
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WALLY-csr-permission-u-01 \
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WALLY-csr-permission-u-01 \
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WALLY-minfo-01 \
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WALLY-misa-01 \
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WALLY-misa-01 \
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WALLY-amo \
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WALLY-lrsc-01 \
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WALLY-lrsc \
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WALLY-status-mie-01 \
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WALLY-status-mie-01 \
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WALLY-trap-sret-01 \
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WALLY-trap-sret-01 \
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target_tests_nosim = \
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target_tests_nosim = \
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WALLY-pma \
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WALLY-pma-01 \
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WALLY-minfo-01 \
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WALLY-mtvec-01 \
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WALLY-mtvec-01 \
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WALLY-stvec-01 \
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WALLY-stvec-01 \
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WALLY-mie-01 \
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WALLY-mie-01 \
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@ -1,20 +0,0 @@
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fffffffe
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00000001
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fffffffb
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fffffffd
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ffffffef
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000007ef
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ffffffbf
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ffffffff
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fffffeff
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fffffd7e
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fffffeff
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000007ff
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ffffefff
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ffffefff
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ffffefff
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ffffefff
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fffeffff
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000007fa
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ffffffff
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ffffffff
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@ -1,175 +0,0 @@
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///////////////////////////////////////////
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// WALLY-AMO.S
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//
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// Tests Atomic AMO instructions
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//
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// David_Harris@hmc.edu 11 March 2021
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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// Adapted from Imperas RISCV-TEST_SUITE
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV32IAF")
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RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",amo)
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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# ---------------------------------------------------------------------------------------------
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# address for test results
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la x6, wally_signature
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la x31, test_data
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# Testcase 0: amoswap.w
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li x7, 1
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amoswap.w x8, x7, (x31)
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lw x9, 0(x31)
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sw x8, 0(x6) # should be fffffffe (sign extended from test data)
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sw x9, 4(x6) # should be 00000001 (stored by amo)
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addi x31, x31, 8
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addi x6, x6, 8
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# Testcase 1: amoadd.w
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li x7, 2
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amoadd.w x8, x7, (x31)
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lw x9, 0(x31)
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sw x8, 0(x6) # should be fffffffb (sign extended from test data)
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sw x9, 4(x6) # should be fffffffd (stored by amo)
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addi x31, x31, 8
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addi x6, x6, 8
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# Testcase 2: amoand.w
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li x7, 0x7ff
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amoand.w x8, x7, (x31)
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lw x9, 0(x31)
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sw x8, 0(x6) # should be ffffffef (sign extended from test data)
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sw x9, 4(x6) # should be 000007ef (stored by amo)
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addi x31, x31, 8
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addi x6, x6, 8
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# Testcase 3: amoor.w
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li x7, 0x44
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amoor.w x8, x7, (x31)
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lw x9, 0(x31)
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sw x8, 0(x6) # should be ffffffbf (sign extended from test data)
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sw x9, 4(x6) # should be ffffffff (stored by amo)
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addi x31, x31, 8
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addi x6, x6, 8
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# Testcase 4: amoxor.w
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li x7, 0x381
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amoxor.w x8, x7, (x31)
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lw x9, 0(x31)
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sw x8, 0(x6) # should be fffffeff (sign extended from test data)
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sw x9, 4(x6) # should be fffffd7e (stored by amo)
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addi x31, x31, 8
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addi x6, x6, 8
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# Testcase 5: amomax.w
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li x7, 0x7ff
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amomax.w x8, x7, (x31)
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lw x9, 0(x31)
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sw x8, 0(x6) # should be fffffeff (sign extended from test data)
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sw x9, 4(x6) # should be 000007ff (stored by amo)
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addi x31, x31, 8
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addi x6, x6, 8
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# Testcase 6: amomin.w
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li x7, 0x7fd
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amomin.w x8, x7, (x31)
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lw x9, 0(x31)
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sw x8, 0(x6) # should be ffffefff (sign extended from test data)
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sw x9, 4(x6) # should be ffffefff (stored by amo)
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addi x31, x31, 8
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addi x6, x6, 8
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# Testcase 7: amomaxu.w
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li x7, 0x7fb
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amomaxu.w x8, x7, (x31)
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lw x9, 0(x31)
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sw x8, 0(x6) # should be ffffefff (sign extended from test data)
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||||||
sw x9, 4(x6) # should be ffffefff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 8
|
|
||||||
|
|
||||||
# Testcase 8: amominu.w
|
|
||||||
li x7, 0x7fa
|
|
||||||
amominu.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sw x8, 0(x6) # should be fffeffff (sign extended from test data)
|
|
||||||
sw x9, 4(x6) # should be 000007fa (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 8
|
|
||||||
# ---------------------------------------------------------------------------------------------
|
|
||||||
RVMODEL_HALT
|
|
||||||
|
|
||||||
RVTEST_DATA_BEGIN
|
|
||||||
.align 8
|
|
||||||
test_data:
|
|
||||||
.dword 0xfffffffdfffffffe
|
|
||||||
.dword 0xfffffff7fffffffb
|
|
||||||
.dword 0xffffffdfffffffef
|
|
||||||
.dword 0xffffff7fffffffbf
|
|
||||||
.dword 0xfffffdfffffffeff
|
|
||||||
.dword 0xfffff7fffffffeff
|
|
||||||
.dword 0x0fffdfffffffefff
|
|
||||||
.dword 0xffff7fffffffefff
|
|
||||||
.dword 0x3ffdfffffffeffff
|
|
||||||
.dword 0xfff7fffffffbffff
|
|
||||||
.dword 0xffdfffffffefffff
|
|
||||||
.dword 0xff7fffffffbfffff
|
|
||||||
.dword 0xfdfffffffeffffff
|
|
||||||
.dword 0xf7fffffffeffffff
|
|
||||||
.dword 0xdfffffffefffffff
|
|
||||||
.dword 0x7fffffffefffffff
|
|
||||||
.dword 0x00000001ffffffff
|
|
||||||
.dword 0x0000000400000002
|
|
||||||
.dword 0x0000001000000008
|
|
||||||
.dword 0x0000004000000020
|
|
||||||
.dword 0x0000010000000080
|
|
||||||
.dword 0x0000040000000200
|
|
||||||
.dword 0x0000100000000800
|
|
||||||
.dword 0x0000400000002000
|
|
||||||
.dword 0x0000000100008000
|
|
||||||
.dword 0x0004000000000002
|
|
||||||
.dword 0x0000001000080000
|
|
||||||
.dword 0x0040000000000020
|
|
||||||
.dword 0x0000010000800000
|
|
||||||
.dword 0x0400000000000200
|
|
||||||
.dword 0x0000100008000000
|
|
||||||
.dword 0x4000000000002000
|
|
||||||
.dword 0x0000000080000000
|
|
||||||
|
|
||||||
#ifdef rvtest_mtrap_routine
|
|
||||||
mtrap_sigptr:
|
|
||||||
.fill 64*(XLEN/32),4,0xdeadbeef
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef rvtest_gpr_save
|
|
||||||
gpr_save:
|
|
||||||
.fill 32*(XLEN/32),4,0xdeadbeef
|
|
||||||
#endif
|
|
||||||
RVTEST_DATA_END
|
|
||||||
|
|
||||||
RVMODEL_DATA_BEGIN
|
|
||||||
# signature output
|
|
||||||
wally_signature:
|
|
||||||
.fill 20, 4, -1
|
|
||||||
RVMODEL_DATA_END
|
|
||||||
@ -28,15 +28,13 @@
|
|||||||
# Description: Makefrag for RV64I architectural tests
|
# Description: Makefrag for RV64I architectural tests
|
||||||
|
|
||||||
rv64i_sc_tests = \
|
rv64i_sc_tests = \
|
||||||
WALLY-mmu-sv39 \
|
WALLY-mmu-sv39-01 \
|
||||||
WALLY-mmu-sv48 \
|
WALLY-mmu-sv48-01 \
|
||||||
WALLY-pmp \
|
WALLY-pmp-01 \
|
||||||
WALLY-minfo-01 \
|
|
||||||
WALLY-csr-permission-s-01 \
|
WALLY-csr-permission-s-01 \
|
||||||
WALLY-csr-permission-u-01 \
|
WALLY-csr-permission-u-01 \
|
||||||
WALLY-misa-01 \
|
WALLY-misa-01 \
|
||||||
WALLY-amo \
|
WALLY-lrsc-01 \
|
||||||
WALLY-lrsc \
|
|
||||||
WALLY-trap-sret-01 \
|
WALLY-trap-sret-01 \
|
||||||
WALLY-status-mie-01 \
|
WALLY-status-mie-01 \
|
||||||
WALLY-status-sie-01 \
|
WALLY-status-sie-01 \
|
||||||
@ -45,8 +43,9 @@ rv64i_sc_tests = \
|
|||||||
|
|
||||||
# Don't simulate these because they rely on SoC features that Spike does not offer.
|
# Don't simulate these because they rely on SoC features that Spike does not offer.
|
||||||
target_tests_nosim = \
|
target_tests_nosim = \
|
||||||
WALLY-pma \
|
WALLY-pma-01 \
|
||||||
WALLY-periph \
|
WALLY-minfo-01 \
|
||||||
|
WALLY-periph-01 \
|
||||||
WALLY-mtvec-01 \
|
WALLY-mtvec-01 \
|
||||||
WALLY-stvec-01 \
|
WALLY-stvec-01 \
|
||||||
WALLY-mie-01 \
|
WALLY-mie-01 \
|
||||||
@ -59,7 +58,11 @@ target_tests_nosim = \
|
|||||||
WALLY-cbom-01 \
|
WALLY-cbom-01 \
|
||||||
WALLY-cboz-01 \
|
WALLY-cboz-01 \
|
||||||
|
|
||||||
|
|
||||||
# unclear why status-fp-enabled and wfi aren't simulating ok
|
# unclear why status-fp-enabled and wfi aren't simulating ok
|
||||||
|
# DH 10/9/23: minfo needs Privileged Spec 1.12 for the mconfigptr register, but
|
||||||
|
# we don't have the right ISA string so it's compiling at 1.11
|
||||||
|
# and Sail throws an illegal instruction exception on csrr mconfigptr
|
||||||
|
|
||||||
rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
|
rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
|
||||||
|
|
||||||
|
|||||||
@ -1,72 +0,0 @@
|
|||||||
fffffffe
|
|
||||||
ffffffff
|
|
||||||
00000001
|
|
||||||
00000000
|
|
||||||
fffffffb
|
|
||||||
ffffffff
|
|
||||||
fffffffd
|
|
||||||
ffffffff
|
|
||||||
ffffffef
|
|
||||||
ffffffff
|
|
||||||
000007ef
|
|
||||||
00000000
|
|
||||||
ffffffbf
|
|
||||||
ffffffff
|
|
||||||
ffffffff
|
|
||||||
ffffffff
|
|
||||||
fffffeff
|
|
||||||
ffffffff
|
|
||||||
fffffd7e
|
|
||||||
ffffffff
|
|
||||||
fffffeff
|
|
||||||
ffffffff
|
|
||||||
000007ff
|
|
||||||
00000000
|
|
||||||
ffffefff
|
|
||||||
ffffffff
|
|
||||||
ffffefff
|
|
||||||
ffffffff
|
|
||||||
ffffefff
|
|
||||||
ffffffff
|
|
||||||
ffffefff
|
|
||||||
ffffffff
|
|
||||||
fffeffff
|
|
||||||
ffffffff
|
|
||||||
000007fa
|
|
||||||
00000000
|
|
||||||
fffbffff
|
|
||||||
fff7ffff
|
|
||||||
00000001
|
|
||||||
00000000
|
|
||||||
ffefffff
|
|
||||||
ffdfffff
|
|
||||||
fff00001
|
|
||||||
ffdfffff
|
|
||||||
ffbfffff
|
|
||||||
ff7fffff
|
|
||||||
000007cf
|
|
||||||
00000000
|
|
||||||
feffffff
|
|
||||||
fdffffff
|
|
||||||
ffffffff
|
|
||||||
fdffffff
|
|
||||||
feffffff
|
|
||||||
f7ffffff
|
|
||||||
fefffc7e
|
|
||||||
f7ffffff
|
|
||||||
efffffff
|
|
||||||
dfffffff
|
|
||||||
000007ff
|
|
||||||
00000000
|
|
||||||
efffffff
|
|
||||||
7fffffff
|
|
||||||
000007fd
|
|
||||||
00000000
|
|
||||||
ffffffff
|
|
||||||
00000001
|
|
||||||
ffffffff
|
|
||||||
00000001
|
|
||||||
00000002
|
|
||||||
00000004
|
|
||||||
000007fa
|
|
||||||
00000000
|
|
||||||
@ -1,258 +0,0 @@
|
|||||||
///////////////////////////////////////////
|
|
||||||
// WALLY-AMO.S
|
|
||||||
//
|
|
||||||
// Tests Atomic AMO instructions
|
|
||||||
//
|
|
||||||
// David_Harris@hmc.edu 10 March 2021
|
|
||||||
//
|
|
||||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
|
||||||
// Adapted from Imperas RISCV-TEST_SUITE
|
|
||||||
//
|
|
||||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
|
||||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
|
||||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
|
||||||
// is furnished to do so, subject to the following conditions:
|
|
||||||
//
|
|
||||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
|
||||||
//
|
|
||||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
||||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
|
||||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
|
||||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|
||||||
///////////////////////////////////////////
|
|
||||||
|
|
||||||
#include "model_test.h"
|
|
||||||
#include "arch_test.h"
|
|
||||||
|
|
||||||
RVTEST_ISA("RV64IAF")
|
|
||||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.A*.F*.*);def TEST_CASE_1=True;",amo)
|
|
||||||
|
|
||||||
.section .text.init
|
|
||||||
.globl rvtest_entry_point
|
|
||||||
rvtest_entry_point:
|
|
||||||
RVMODEL_BOOT
|
|
||||||
|
|
||||||
# ---------------------------------------------------------------------------------------------
|
|
||||||
# Addresses for test data and results
|
|
||||||
la x6, wally_signature
|
|
||||||
la x31, test_data
|
|
||||||
|
|
||||||
# Testcase 0: amoswap.w
|
|
||||||
li x7, 1
|
|
||||||
amoswap.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be fffffffffffffffe (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be 0000000000000001 (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 1: amoadd.w
|
|
||||||
li x7, 2
|
|
||||||
amoadd.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be fffffffffffffffb (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be fffffffffffffffd (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 2: amoand.w
|
|
||||||
li x7, 0x7ff
|
|
||||||
amoand.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be ffffffffffffffef (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007ef (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 3: amoor.w
|
|
||||||
li x7, 0x44
|
|
||||||
amoor.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be ffffffffffffffbf (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be ffffffffffffffff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 4: amoxor.w
|
|
||||||
li x7, 0x381
|
|
||||||
amoxor.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be fffffffffffffeff (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be fffffffffffffd7e (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 5: amomax.w
|
|
||||||
li x7, 0x7ff
|
|
||||||
amomax.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be fffffffffffffeff (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007ff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 6: amomin.w
|
|
||||||
li x7, 0x7fd
|
|
||||||
amomin.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be ffffffffffffefff (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be ffffffffffffefff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 7: amomaxu.w
|
|
||||||
li x7, 0x7fb
|
|
||||||
amomaxu.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be ffffffffffffefff (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be ffffffffffffefff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 8: amominu.w
|
|
||||||
li x7, 0x7fa
|
|
||||||
amominu.w x8, x7, (x31)
|
|
||||||
lw x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be fffffffffffeffff (sign extended from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007fa (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
|
|
||||||
# Testcase 9: amoswap.d
|
|
||||||
li x7, 1
|
|
||||||
amoswap.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0xfff7fffffffbffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 0000000000000001 (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 10: amoadd.d
|
|
||||||
li x7, 2
|
|
||||||
amoadd.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0xffdfffffffefffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 0xffdffffffff00001 (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 11: amoand.d
|
|
||||||
li x7, 0x7cf
|
|
||||||
amoand.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0xff7fffffffbfffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007cf (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 12: amoor.d
|
|
||||||
li x7, 0x0d000011
|
|
||||||
amoor.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0xfdfffffffeffffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 0xfdffffffffffffff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 13: amoxor.d
|
|
||||||
li x7, 0x381
|
|
||||||
amoxor.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0xf7fffffffeffffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 0xf7fffffffefffc7e (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 14: amomax.d
|
|
||||||
li x7, 0x7ff
|
|
||||||
amomax.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0xdfffffffefffffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007ff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 15: amomin.d
|
|
||||||
li x7, 0x7fd
|
|
||||||
amomin.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0x7fffffffefffffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007fd (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 16: amomaxu.d
|
|
||||||
li x7, 0x7fb
|
|
||||||
amomaxu.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0x00000001ffffffff (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 0x00000001ffffffff (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# Testcase 17: amominu.d
|
|
||||||
li x7, 0x7fa
|
|
||||||
amominu.d x8, x7, (x31)
|
|
||||||
ld x9, 0(x31)
|
|
||||||
sd x8, 0(x6) # should be 0x0000000400000002 (directly read from test data)
|
|
||||||
sd x9, 8(x6) # should be 00000000000007fa (stored by amo)
|
|
||||||
addi x31, x31, 8
|
|
||||||
addi x6, x6, 16
|
|
||||||
|
|
||||||
# ---------------------------------------------------------------------------------------------
|
|
||||||
RVMODEL_HALT
|
|
||||||
|
|
||||||
RVTEST_DATA_BEGIN
|
|
||||||
.align 8
|
|
||||||
test_data:
|
|
||||||
.dword 0xfffffffdfffffffe
|
|
||||||
.dword 0xfffffff7fffffffb
|
|
||||||
.dword 0xffffffdfffffffef
|
|
||||||
.dword 0xffffff7fffffffbf
|
|
||||||
.dword 0xfffffdfffffffeff
|
|
||||||
.dword 0xfffff7fffffffeff
|
|
||||||
.dword 0x0fffdfffffffefff
|
|
||||||
.dword 0xffff7fffffffefff
|
|
||||||
.dword 0x3ffdfffffffeffff
|
|
||||||
.dword 0xfff7fffffffbffff
|
|
||||||
.dword 0xffdfffffffefffff
|
|
||||||
.dword 0xff7fffffffbfffff
|
|
||||||
.dword 0xfdfffffffeffffff
|
|
||||||
.dword 0xf7fffffffeffffff
|
|
||||||
.dword 0xdfffffffefffffff
|
|
||||||
.dword 0x7fffffffefffffff
|
|
||||||
.dword 0x00000001ffffffff
|
|
||||||
.dword 0x0000000400000002
|
|
||||||
.dword 0x0000001000000008
|
|
||||||
.dword 0x0000004000000020
|
|
||||||
.dword 0x0000010000000080
|
|
||||||
.dword 0x0000040000000200
|
|
||||||
.dword 0x0000100000000800
|
|
||||||
.dword 0x0000400000002000
|
|
||||||
.dword 0x0000000100008000
|
|
||||||
.dword 0x0004000000000002
|
|
||||||
.dword 0x0000001000080000
|
|
||||||
.dword 0x0040000000000020
|
|
||||||
.dword 0x0000010000800000
|
|
||||||
.dword 0x0400000000000200
|
|
||||||
.dword 0x0000100008000000
|
|
||||||
.dword 0x4000000000002000
|
|
||||||
.dword 0x0000000080000000
|
|
||||||
RVTEST_DATA_END
|
|
||||||
|
|
||||||
RVMODEL_DATA_BEGIN
|
|
||||||
# signature output
|
|
||||||
wally_signature:
|
|
||||||
.fill 36, 8, -1
|
|
||||||
|
|
||||||
#ifdef rvtest_mtrap_routine
|
|
||||||
#mtrap_sigptr:
|
|
||||||
# .fill 64*(XLEN/32),4,0xdeadbeef
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef rvtest_gpr_save
|
|
||||||
#gpr_save:
|
|
||||||
# .fill 32*(XLEN/32),4,0xdeadbeef
|
|
||||||
#endif
|
|
||||||
RVMODEL_DATA_END
|
|
||||||
Loading…
Reference in New Issue
Block a user