From ac4216b43d434ce0e2603f68d39e4356dc0247f7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 16 Oct 2023 10:25:45 -0700 Subject: [PATCH] Incorporated new AMO tests from riscv-arch-test --- sim/regression-wally | 4 +- sim/rv64gc_CacheSim.py | 2 + testbench/testbench.sv | 6 +- testbench/tests.vh | 39 ++- .../rv32i_m/privilege/Makefrag | 9 +- .../references/WALLY-amo-01.reference_output | 20 -- .../rv32i_m/privilege/src/WALLY-amo-01.S | 175 ------------ .../rv64i_m/privilege/Makefrag | 19 +- .../references/WALLY-amo-01.reference_output | 72 ----- .../rv64i_m/privilege/src/WALLY-amo-01.S | 258 ------------------ 10 files changed, 60 insertions(+), 544 deletions(-) delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-amo-01.reference_output delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo-01.S delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-amo-01.reference_output delete mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo-01.S diff --git a/sim/regression-wally b/sim/regression-wally index 1569abd77..006718701 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -85,7 +85,7 @@ for test in tests64i: configs.append(tc) tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused -tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"] +tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"] for test in tests32gc: tc = TestCase( name=test, @@ -133,7 +133,7 @@ for test in ahbTests: configs.append(tc) tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", - "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] + "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zi", "wally64a", "wally64periph", "wally64priv"] if (coverage): # delete all but 64gc tests when running coverage configs = [] tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 56a76c9ac..42f21c8c6 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -52,6 +52,8 @@ tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "imperas64f", "imperas64d", "imperas64c", "imperas64i"] +# arch64i is the most interesting case. Uncomment line below to run just that case +tests64gc = ["arch64i"] cachetypes = ["ICache", "DCache"] simdir = os.path.expanduser("~/cvw/sim") diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 74077e547..ebfc56c5f 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -38,8 +38,8 @@ module testbench; parameter TEST="none"; parameter PrintHPMCounters=1; parameter BPRED_LOGGER=0; - parameter I_CACHE_ADDR_LOGGER=0; - parameter D_CACHE_ADDR_LOGGER=0; + parameter I_CACHE_ADDR_LOGGER=1; + parameter D_CACHE_ADDR_LOGGER=1; `include "parameter-defs.vh" @@ -98,6 +98,7 @@ module testbench; if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; else tests = {arch64c}; "arch64m": if (P.M_SUPPORTED) tests = arch64m; + "arch64a": if (P.A_SUPPORTED) tests = arch64a; "arch64f": if (P.F_SUPPORTED) tests = arch64f; "arch64d": if (P.D_SUPPORTED) tests = arch64d; "arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma; @@ -131,6 +132,7 @@ module testbench; if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; else tests = {arch32c}; "arch32m": if (P.M_SUPPORTED) tests = arch32m; + "arch32a": if (P.A_SUPPORTED) tests = arch32a; "arch32f": if (P.F_SUPPORTED) tests = arch32f; "arch32d": if (P.D_SUPPORTED) tests = arch32d; "arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma; diff --git a/testbench/tests.vh b/testbench/tests.vh index 8ba4ce8d1..5e4f607cb 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -864,13 +864,11 @@ string imperas32f[] = '{ string wally64a[] = '{ `WALLYTEST, - "rv64i_m/privilege/src/WALLY-amo-01.S", "rv64i_m/privilege/src/WALLY-lrsc-01.S" }; string wally32a[] = '{ `WALLYTEST, - "rv32i_m/privilege/src/WALLY-amo-01.S", "rv32i_m/privilege/src/WALLY-lrsc-01.S" }; @@ -902,6 +900,20 @@ string imperas32f[] = '{ "rv64i_m/Zifencei/src/Fencei.S" }; + string arch32a[] = '{ + `RISCVARCHTEST, + "rv32i_m/A/src/amoadd.w-01.S", + "rv32i_m/A/src/amoand.w-01.S", + "rv32i_m/A/src/amomax.w-01.S", + "rv32i_m/A/src/amomaxu.w-01.S", + "rv32i_m/A/src/amomin.w-01.S", + "rv32i_m/A/src/amominu.w-01.S", + "rv32i_m/A/src/amoor.w-01.S", + "rv32i_m/A/src/amoswap.w-01.S", + "rv32i_m/A/src/amoxor.w-01.S" + }; + + string arch32zi[] = '{ `RISCVARCHTEST, "rv32i_m/Zifencei/src/Fencei.S" @@ -972,6 +984,28 @@ string imperas32f[] = '{ "rv64i_m/M/src/remw-01.S" }; + string arch64a[] = '{ + `RISCVARCHTEST, + "rv64i_m/A/src/amoadd.w-01.S", + "rv64i_m/A/src/amoand.w-01.S", + "rv64i_m/A/src/amomax.w-01.S", + "rv64i_m/A/src/amomaxu.w-01.S", + "rv64i_m/A/src/amomin.w-01.S", + "rv64i_m/A/src/amominu.w-01.S", + "rv64i_m/A/src/amoor.w-01.S", + "rv64i_m/A/src/amoswap.w-01.S", + "rv64i_m/A/src/amoxor.w-01.S", + "rv64i_m/A/src/amoadd.d-01.S", + "rv64i_m/A/src/amoand.d-01.S", + "rv64i_m/A/src/amomax.d-01.S", + "rv64i_m/A/src/amomaxu.d-01.S", + "rv64i_m/A/src/amomin.d-01.S", + "rv64i_m/A/src/amominu.d-01.S", + "rv64i_m/A/src/amoor.d-01.S", + "rv64i_m/A/src/amoswap.d-01.S", + "rv64i_m/A/src/amoxor.d-01.S" + }; + string arch64c[] = '{ `RISCVARCHTEST, "rv64i_m/C/src/cadd-01.S", @@ -1936,6 +1970,7 @@ string arch64zbs[] = '{ string wally64priv[] = '{ `WALLYTEST, + "rv64i_m/privilege/src/WALLY-minfo-01.S", "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S", "rv64i_m/privilege/src/WALLY-cboz-01.S", "rv64i_m/privilege/src/WALLY-cbom-01.S", diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag index 837668c3c..cb28d7cf4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag @@ -29,19 +29,18 @@ rv32i_sc_tests = \ WALLY-mmu-sv32 \ - WALLY-pmp \ + WALLY-pm-01 \ WALLY-csr-permission-s-01 \ WALLY-csr-permission-u-01 \ - WALLY-minfo-01 \ WALLY-misa-01 \ - WALLY-amo \ - WALLY-lrsc \ + WALLY-lrsc-01 \ WALLY-status-mie-01 \ WALLY-trap-sret-01 \ target_tests_nosim = \ - WALLY-pma \ + WALLY-pma-01 \ + WALLY-minfo-01 \ WALLY-mtvec-01 \ WALLY-stvec-01 \ WALLY-mie-01 \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-amo-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-amo-01.reference_output deleted file mode 100644 index 6d2c17395..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-amo-01.reference_output +++ /dev/null @@ -1,20 +0,0 @@ -fffffffe -00000001 -fffffffb -fffffffd -ffffffef -000007ef -ffffffbf -ffffffff -fffffeff -fffffd7e -fffffeff -000007ff -ffffefff -ffffefff -ffffefff -ffffefff -fffeffff -000007fa -ffffffff -ffffffff diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo-01.S deleted file mode 100644 index 8a1906585..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo-01.S +++ /dev/null @@ -1,175 +0,0 @@ -/////////////////////////////////////////// -// WALLY-AMO.S -// -// Tests Atomic AMO instructions -// -// David_Harris@hmc.edu 11 March 2021 -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// Adapted from Imperas RISCV-TEST_SUITE -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -#include "model_test.h" -#include "arch_test.h" - -RVTEST_ISA("RV32IAF") -RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",amo) - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT - - # --------------------------------------------------------------------------------------------- - # address for test results - la x6, wally_signature - la x31, test_data - - # Testcase 0: amoswap.w - li x7, 1 - amoswap.w x8, x7, (x31) - lw x9, 0(x31) - sw x8, 0(x6) # should be fffffffe (sign extended from test data) - sw x9, 4(x6) # should be 00000001 (stored by amo) - addi x31, x31, 8 - addi x6, x6, 8 - - # Testcase 1: amoadd.w - li x7, 2 - amoadd.w x8, x7, (x31) - lw x9, 0(x31) - sw x8, 0(x6) # should be fffffffb (sign extended from test data) - sw x9, 4(x6) # should be fffffffd (stored by amo) - addi x31, x31, 8 - addi x6, x6, 8 - - # Testcase 2: amoand.w - li x7, 0x7ff - amoand.w x8, x7, (x31) - lw x9, 0(x31) - sw x8, 0(x6) # should be ffffffef (sign extended from test data) - sw x9, 4(x6) # should be 000007ef (stored by amo) - addi x31, x31, 8 - addi x6, x6, 8 - - # Testcase 3: amoor.w - li x7, 0x44 - amoor.w x8, x7, (x31) - lw x9, 0(x31) - sw x8, 0(x6) # should be ffffffbf (sign extended from test data) - sw x9, 4(x6) # should be ffffffff (stored by amo) - addi x31, x31, 8 - addi x6, x6, 8 - - # Testcase 4: amoxor.w - li x7, 0x381 - amoxor.w x8, x7, (x31) - lw x9, 0(x31) - sw x8, 0(x6) # should be fffffeff (sign extended from test data) - sw x9, 4(x6) # should be fffffd7e (stored by amo) - addi x31, x31, 8 - addi x6, x6, 8 - - # Testcase 5: amomax.w - li x7, 0x7ff - amomax.w x8, x7, (x31) - lw x9, 0(x31) - sw x8, 0(x6) # should be fffffeff (sign extended from test data) - sw x9, 4(x6) # should be 000007ff (stored by amo) - addi x31, x31, 8 - addi x6, x6, 8 - - # Testcase 6: amomin.w - li x7, 0x7fd - amomin.w x8, x7, (x31) - lw x9, 0(x31) - sw x8, 0(x6) # should be ffffefff (sign extended from test data) - sw x9, 4(x6) # should be ffffefff (stored by amo) - addi x31, x31, 8 - addi x6, x6, 8 - - # Testcase 7: amomaxu.w - li x7, 0x7fb - amomaxu.w x8, x7, (x31) - lw x9, 0(x31) - sw x8, 0(x6) # should be ffffefff (sign extended from test data) - sw x9, 4(x6) # should be ffffefff (stored by amo) - addi x31, x31, 8 - addi x6, x6, 8 - - # Testcase 8: amominu.w - li x7, 0x7fa - amominu.w x8, x7, (x31) - lw x9, 0(x31) - sw x8, 0(x6) # should be fffeffff (sign extended from test data) - sw x9, 4(x6) # should be 000007fa (stored by amo) - addi x31, x31, 8 - addi x6, x6, 8 - # --------------------------------------------------------------------------------------------- -RVMODEL_HALT - -RVTEST_DATA_BEGIN - .align 8 -test_data: - .dword 0xfffffffdfffffffe - .dword 0xfffffff7fffffffb - .dword 0xffffffdfffffffef - .dword 0xffffff7fffffffbf - .dword 0xfffffdfffffffeff - .dword 0xfffff7fffffffeff - .dword 0x0fffdfffffffefff - .dword 0xffff7fffffffefff - .dword 0x3ffdfffffffeffff - .dword 0xfff7fffffffbffff - .dword 0xffdfffffffefffff - .dword 0xff7fffffffbfffff - .dword 0xfdfffffffeffffff - .dword 0xf7fffffffeffffff - .dword 0xdfffffffefffffff - .dword 0x7fffffffefffffff - .dword 0x00000001ffffffff - .dword 0x0000000400000002 - .dword 0x0000001000000008 - .dword 0x0000004000000020 - .dword 0x0000010000000080 - .dword 0x0000040000000200 - .dword 0x0000100000000800 - .dword 0x0000400000002000 - .dword 0x0000000100008000 - .dword 0x0004000000000002 - .dword 0x0000001000080000 - .dword 0x0040000000000020 - .dword 0x0000010000800000 - .dword 0x0400000000000200 - .dword 0x0000100008000000 - .dword 0x4000000000002000 - .dword 0x0000000080000000 - -#ifdef rvtest_mtrap_routine -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -#endif - -#ifdef rvtest_gpr_save -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef -#endif -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -# signature output -wally_signature: -.fill 20, 4, -1 -RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index bc5f454bb..bd522e9a4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -28,15 +28,13 @@ # Description: Makefrag for RV64I architectural tests rv64i_sc_tests = \ - WALLY-mmu-sv39 \ - WALLY-mmu-sv48 \ - WALLY-pmp \ - WALLY-minfo-01 \ + WALLY-mmu-sv39-01 \ + WALLY-mmu-sv48-01 \ + WALLY-pmp-01 \ WALLY-csr-permission-s-01 \ WALLY-csr-permission-u-01 \ WALLY-misa-01 \ - WALLY-amo \ - WALLY-lrsc \ + WALLY-lrsc-01 \ WALLY-trap-sret-01 \ WALLY-status-mie-01 \ WALLY-status-sie-01 \ @@ -45,8 +43,9 @@ rv64i_sc_tests = \ # Don't simulate these because they rely on SoC features that Spike does not offer. target_tests_nosim = \ - WALLY-pma \ - WALLY-periph \ + WALLY-pma-01 \ + WALLY-minfo-01 \ + WALLY-periph-01 \ WALLY-mtvec-01 \ WALLY-stvec-01 \ WALLY-mie-01 \ @@ -59,7 +58,11 @@ target_tests_nosim = \ WALLY-cbom-01 \ WALLY-cboz-01 \ + # unclear why status-fp-enabled and wfi aren't simulating ok +# DH 10/9/23: minfo needs Privileged Spec 1.12 for the mconfigptr register, but +# we don't have the right ISA string so it's compiling at 1.11 +# and Sail throws an illegal instruction exception on csrr mconfigptr rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-amo-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-amo-01.reference_output deleted file mode 100644 index edce96fe8..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-amo-01.reference_output +++ /dev/null @@ -1,72 +0,0 @@ -fffffffe -ffffffff -00000001 -00000000 -fffffffb -ffffffff -fffffffd -ffffffff -ffffffef -ffffffff -000007ef -00000000 -ffffffbf -ffffffff -ffffffff -ffffffff -fffffeff -ffffffff -fffffd7e -ffffffff -fffffeff -ffffffff -000007ff -00000000 -ffffefff -ffffffff -ffffefff -ffffffff -ffffefff -ffffffff -ffffefff -ffffffff -fffeffff -ffffffff -000007fa -00000000 -fffbffff -fff7ffff -00000001 -00000000 -ffefffff -ffdfffff -fff00001 -ffdfffff -ffbfffff -ff7fffff -000007cf -00000000 -feffffff -fdffffff -ffffffff -fdffffff -feffffff -f7ffffff -fefffc7e -f7ffffff -efffffff -dfffffff -000007ff -00000000 -efffffff -7fffffff -000007fd -00000000 -ffffffff -00000001 -ffffffff -00000001 -00000002 -00000004 -000007fa -00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo-01.S deleted file mode 100644 index 1d246a54b..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo-01.S +++ /dev/null @@ -1,258 +0,0 @@ -/////////////////////////////////////////// -// WALLY-AMO.S -// -// Tests Atomic AMO instructions -// -// David_Harris@hmc.edu 10 March 2021 -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// Adapted from Imperas RISCV-TEST_SUITE -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -#include "model_test.h" -#include "arch_test.h" - -RVTEST_ISA("RV64IAF") -RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.A*.F*.*);def TEST_CASE_1=True;",amo) - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT - - # --------------------------------------------------------------------------------------------- - # Addresses for test data and results - la x6, wally_signature - la x31, test_data - - # Testcase 0: amoswap.w - li x7, 1 - amoswap.w x8, x7, (x31) - lw x9, 0(x31) - sd x8, 0(x6) # should be fffffffffffffffe (sign extended from test data) - sd x9, 8(x6) # should be 0000000000000001 (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 1: amoadd.w - li x7, 2 - amoadd.w x8, x7, (x31) - lw x9, 0(x31) - sd x8, 0(x6) # should be fffffffffffffffb (sign extended from test data) - sd x9, 8(x6) # should be fffffffffffffffd (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 2: amoand.w - li x7, 0x7ff - amoand.w x8, x7, (x31) - lw x9, 0(x31) - sd x8, 0(x6) # should be ffffffffffffffef (sign extended from test data) - sd x9, 8(x6) # should be 00000000000007ef (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 3: amoor.w - li x7, 0x44 - amoor.w x8, x7, (x31) - lw x9, 0(x31) - sd x8, 0(x6) # should be ffffffffffffffbf (sign extended from test data) - sd x9, 8(x6) # should be ffffffffffffffff (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 4: amoxor.w - li x7, 0x381 - amoxor.w x8, x7, (x31) - lw x9, 0(x31) - sd x8, 0(x6) # should be fffffffffffffeff (sign extended from test data) - sd x9, 8(x6) # should be fffffffffffffd7e (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 5: amomax.w - li x7, 0x7ff - amomax.w x8, x7, (x31) - lw x9, 0(x31) - sd x8, 0(x6) # should be fffffffffffffeff (sign extended from test data) - sd x9, 8(x6) # should be 00000000000007ff (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 6: amomin.w - li x7, 0x7fd - amomin.w x8, x7, (x31) - lw x9, 0(x31) - sd x8, 0(x6) # should be ffffffffffffefff (sign extended from test data) - sd x9, 8(x6) # should be ffffffffffffefff (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 7: amomaxu.w - li x7, 0x7fb - amomaxu.w x8, x7, (x31) - lw x9, 0(x31) - sd x8, 0(x6) # should be ffffffffffffefff (sign extended from test data) - sd x9, 8(x6) # should be ffffffffffffefff (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 8: amominu.w - li x7, 0x7fa - amominu.w x8, x7, (x31) - lw x9, 0(x31) - sd x8, 0(x6) # should be fffffffffffeffff (sign extended from test data) - sd x9, 8(x6) # should be 00000000000007fa (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - - # Testcase 9: amoswap.d - li x7, 1 - amoswap.d x8, x7, (x31) - ld x9, 0(x31) - sd x8, 0(x6) # should be 0xfff7fffffffbffff (directly read from test data) - sd x9, 8(x6) # should be 0000000000000001 (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 10: amoadd.d - li x7, 2 - amoadd.d x8, x7, (x31) - ld x9, 0(x31) - sd x8, 0(x6) # should be 0xffdfffffffefffff (directly read from test data) - sd x9, 8(x6) # should be 0xffdffffffff00001 (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 11: amoand.d - li x7, 0x7cf - amoand.d x8, x7, (x31) - ld x9, 0(x31) - sd x8, 0(x6) # should be 0xff7fffffffbfffff (directly read from test data) - sd x9, 8(x6) # should be 00000000000007cf (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 12: amoor.d - li x7, 0x0d000011 - amoor.d x8, x7, (x31) - ld x9, 0(x31) - sd x8, 0(x6) # should be 0xfdfffffffeffffff (directly read from test data) - sd x9, 8(x6) # should be 0xfdffffffffffffff (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 13: amoxor.d - li x7, 0x381 - amoxor.d x8, x7, (x31) - ld x9, 0(x31) - sd x8, 0(x6) # should be 0xf7fffffffeffffff (directly read from test data) - sd x9, 8(x6) # should be 0xf7fffffffefffc7e (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 14: amomax.d - li x7, 0x7ff - amomax.d x8, x7, (x31) - ld x9, 0(x31) - sd x8, 0(x6) # should be 0xdfffffffefffffff (directly read from test data) - sd x9, 8(x6) # should be 00000000000007ff (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 15: amomin.d - li x7, 0x7fd - amomin.d x8, x7, (x31) - ld x9, 0(x31) - sd x8, 0(x6) # should be 0x7fffffffefffffff (directly read from test data) - sd x9, 8(x6) # should be 00000000000007fd (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 16: amomaxu.d - li x7, 0x7fb - amomaxu.d x8, x7, (x31) - ld x9, 0(x31) - sd x8, 0(x6) # should be 0x00000001ffffffff (directly read from test data) - sd x9, 8(x6) # should be 0x00000001ffffffff (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # Testcase 17: amominu.d - li x7, 0x7fa - amominu.d x8, x7, (x31) - ld x9, 0(x31) - sd x8, 0(x6) # should be 0x0000000400000002 (directly read from test data) - sd x9, 8(x6) # should be 00000000000007fa (stored by amo) - addi x31, x31, 8 - addi x6, x6, 16 - - # --------------------------------------------------------------------------------------------- -RVMODEL_HALT - -RVTEST_DATA_BEGIN - .align 8 -test_data: - .dword 0xfffffffdfffffffe - .dword 0xfffffff7fffffffb - .dword 0xffffffdfffffffef - .dword 0xffffff7fffffffbf - .dword 0xfffffdfffffffeff - .dword 0xfffff7fffffffeff - .dword 0x0fffdfffffffefff - .dword 0xffff7fffffffefff - .dword 0x3ffdfffffffeffff - .dword 0xfff7fffffffbffff - .dword 0xffdfffffffefffff - .dword 0xff7fffffffbfffff - .dword 0xfdfffffffeffffff - .dword 0xf7fffffffeffffff - .dword 0xdfffffffefffffff - .dword 0x7fffffffefffffff - .dword 0x00000001ffffffff - .dword 0x0000000400000002 - .dword 0x0000001000000008 - .dword 0x0000004000000020 - .dword 0x0000010000000080 - .dword 0x0000040000000200 - .dword 0x0000100000000800 - .dword 0x0000400000002000 - .dword 0x0000000100008000 - .dword 0x0004000000000002 - .dword 0x0000001000080000 - .dword 0x0040000000000020 - .dword 0x0000010000800000 - .dword 0x0400000000000200 - .dword 0x0000100008000000 - .dword 0x4000000000002000 - .dword 0x0000000080000000 -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -# signature output -wally_signature: -.fill 36, 8, -1 - -#ifdef rvtest_mtrap_routine -#mtrap_sigptr: -# .fill 64*(XLEN/32),4,0xdeadbeef -#endif - -#ifdef rvtest_gpr_save -#gpr_save: -# .fill 32*(XLEN/32),4,0xdeadbeef -#endif -RVMODEL_DATA_END