Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Update ram1p1rwe (ce & we) coverage exlusion explanation

Browse Source
This commit is contained in:
Alec Vercruysse 2023-04-05 14:54:58 -07:00
parent 570e86afc3
commit ac3569d75c
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/generic/mem/ram1p1rwe.sv
View File

@ -5,6 +5,8 @@
// Created: 04 April 2023 // Created: 04 April 2023
// //
// Purpose: ram1p1wre, but without byte-enable. Used for icache data. // Purpose: ram1p1wre, but without byte-enable. Used for icache data.
// Be careful using this module, since coverage is turned off for (ce & we).
// In read-only caches, we never get (we=1, ce=0), so this waiver is needed.
// //
// Documentation: // Documentation:
// //
@ -85,8 +87,7 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
// coverage off // coverage off
// ce only goes low when cachefsm is in READY state and Flush is asserted. // ce only goes low when cachefsm is in READY state and Flush is asserted.
// for read-only caches, we only goes high in the STATE_WRITE_LINE cachefsm state. // for read-only caches, we only goes high in the STATE_WRITE_LINE cachefsm state.
// so we can never get we=1, ce=0 for I$. Note that turning off coverage here // so we can never get we=1, ce=0 for I$.
// might miss some cases for D$, however, when we might go high due to a store.
if (ce & we) if (ce & we)
// coverage on // coverage on
for(i = 0; i < WIDTH/8; i++) for(i = 0; i < WIDTH/8; i++)