From ac3569d75ca4c4aebda19df6c236b43614285fae Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Wed, 5 Apr 2023 14:54:58 -0700 Subject: [PATCH] Update ram1p1rwe (ce & we) coverage exlusion explanation --- src/generic/mem/ram1p1rwe.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index 8a2f971e9..480ad3b45 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -5,6 +5,8 @@ // Created: 04 April 2023 // // Purpose: ram1p1wre, but without byte-enable. Used for icache data. +// Be careful using this module, since coverage is turned off for (ce & we). +// In read-only caches, we never get (we=1, ce=0), so this waiver is needed. // // Documentation: // @@ -85,8 +87,7 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) ( // coverage off // ce only goes low when cachefsm is in READY state and Flush is asserted. // for read-only caches, we only goes high in the STATE_WRITE_LINE cachefsm state. - // so we can never get we=1, ce=0 for I$. Note that turning off coverage here - // might miss some cases for D$, however, when we might go high due to a store. + // so we can never get we=1, ce=0 for I$. if (ce & we) // coverage on for(i = 0; i < WIDTH/8; i++)