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Fixed bug in SPI with the help of Naiche and Jacob. Have yet to test

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if SPI will now run correctly with div=0 (SYSTEMCLOCK/2), but the SPI
flash card now correctly loads into the Linux OS and mount and is
reading and writting without error.
This commit is contained in:
Rose Thompson 2024-09-04 17:51:48 -07:00
parent 8c99e28c8b
commit ac047a04fa
1 changed files with 9 additions and 1 deletions
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10
src/uncore/spi_apb.sv
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@ -90,6 +90,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark; logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark;
logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty; logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty;
logic TransmitFIFOWriteIncrement; logic TransmitFIFOWriteIncrement;
logic ReceiveFiFoWriteInc;
logic ReceiveFIFOReadIncrement; logic ReceiveFIFOReadIncrement;
logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty; logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty;
logic [7:0] TransmitFIFOReadData; logic [7:0] TransmitFIFOReadData;
@ -301,7 +302,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
// Tx/Rx FIFOs // Tx/Rx FIFOs
spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitFIFOReadIncrement, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0], spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitFIFOReadIncrement, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0],
TransmitFIFOReadData[7:0], TransmitFIFOWriteFull, TransmitFIFOReadEmpty, TransmitWriteMark, TransmitReadMark); TransmitFIFOReadData[7:0], TransmitFIFOWriteFull, TransmitFIFOReadEmpty, TransmitWriteMark, TransmitReadMark);
spi_fifo #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveShiftFullDelay, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel, spi_fifo #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveFiFoWriteInc, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel,
ReceiveData[7:0], ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty, RecieveWriteMark, RecieveReadMark); ReceiveData[7:0], ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty, RecieveWriteMark, RecieveReadMark);
always_ff @(posedge PCLK) always_ff @(posedge PCLK)
@ -311,6 +312,13 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
always_ff @(posedge PCLK) always_ff @(posedge PCLK)
if (~PRESETn) ReceiveShiftFullDelay <= 1'b0; if (~PRESETn) ReceiveShiftFullDelay <= 1'b0;
else if (SCLKenable) ReceiveShiftFullDelay <= ReceiveShiftFull; else if (SCLKenable) ReceiveShiftFullDelay <= ReceiveShiftFull;
assign ReceiveFiFoTakingData = ReceiveFiFoWriteInc & ~ReceiveFIFOWriteFull;
always_ff @(posedge PCLK)
if (~PRESETn) ReceiveFiFoWriteInc <= 1'b0;
else if (SCLKenable & ReceiveShiftFull) ReceiveFiFoWriteInc <= 1'b1;
else if (SCLKenable & ReceiveFiFoTakingData) ReceiveFiFoWriteInc <= 1'b0;
always_ff @(posedge PCLK) always_ff @(posedge PCLK)
if (~PRESETn) ReceiveShiftFullDelayPCLK <= 1'b0; if (~PRESETn) ReceiveShiftFullDelayPCLK <= 1'b0;
else if (SCLKenableEarly) ReceiveShiftFullDelayPCLK <= ReceiveShiftFull; else if (SCLKenableEarly) ReceiveShiftFullDelayPCLK <= ReceiveShiftFull;