From ab1ee3d69b4f72a1d54d13695203467a27fe299b Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 19 Jun 2024 09:40:35 -0700
Subject: [PATCH] Removed *** from IFU, lrcs.

---
 fpga/src/fpgaTopArtyA7.sv |  1 -
 sim/vcs/run_vcs           |  2 +-
 src/ebu/buscachefsm.sv    |  1 -
 src/generic/clockgater.sv | 50 ---------------------------------------
 src/lsu/lrsc.sv           |  1 -
 5 files changed, 1 insertion(+), 54 deletions(-)
 delete mode 100644 src/generic/clockgater.sv

diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv
index 676eaae79..9ddf958a7 100644
--- a/fpga/src/fpgaTopArtyA7.sv
+++ b/fpga/src/fpgaTopArtyA7.sv
@@ -1048,7 +1048,6 @@ module fpgaTop
      .sys_rst(resetn),    // omg. this is active low?!?!?? 
      .mmcm_locked(mmcm_locked),
 
-     // *** What are these? 
      .app_sr_req(1'b0),  // reserved command
      .app_ref_req(1'b0), // refresh command
      .app_zq_req(1'b0),  // recalibrate command
diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs
index 597907a8e..5601e57b2 100755
--- a/sim/vcs/run_vcs
+++ b/sim/vcs/run_vcs
@@ -86,7 +86,7 @@ INCLUDE_DIRS=$(find ${SRC} -type d | xargs -I {} echo -n "{} ")
 INCLUDE_PATH="+incdir+${CFG}/${CONFIG_VARIANT} +incdir+${CFG}/deriv/${CONFIG_VARIANT} +incdir+${CFG}/shared +incdir+../../tests +define+ +incdir+${TB} ${SRC}/cvw.sv +incdir+${SRC}"
 
 # Prepare RTL files avoiding certain paths
-RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/clockgater.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x64.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x32.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_2048x64.sv")  ${TB}/testbench.sv $(find ${TB}/common -name "*.sv" ! -path "${TB}/common/wallyTracer.sv")"
+RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x64.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x32.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_2048x64.sv")  ${TB}/testbench.sv $(find ${TB}/common -name "*.sv" ! -path "${TB}/common/wallyTracer.sv")"
 
 # Simulation and Coverage Commands
 OUTPUT="sim_out"
diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv
index 5f39e1602..623d17975 100644
--- a/src/ebu/buscachefsm.sv
+++ b/src/ebu/buscachefsm.sv
@@ -128,7 +128,6 @@ module buscachefsm #(
   assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK;
 
   assign BusStall = (CurrState == ADR_PHASE & ((|BusRW) | (|CacheBusRW) | BusCMOZero)) |
-                    //(CurrState == DATA_PHASE & ~BusRW[0]) |  // *** replace the next line with this.  Fails uart test but i think it's a test problem not a hardware problem.
                     (CurrState == DATA_PHASE) | 
                     (CurrState == ATOMIC_PHASE) |
                     (CurrState == ATOMIC_READ_DATA_PHASE) |
diff --git a/src/generic/clockgater.sv b/src/generic/clockgater.sv
deleted file mode 100644
index 48282ccfa..000000000
--- a/src/generic/clockgater.sv
+++ /dev/null
@@ -1,50 +0,0 @@
-///////////////////////////////////////////
-// clockgater.sv
-//
-// Written: Ross Thompson 9 January 2021
-// Modified: 
-//
-// Purpose: Clock gater model. Must use standard cell for synthesis.
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module clockgater #(parameter FPGA) (
-  input  logic E,
-  input  logic SE,
-  input  logic CLK,
-  output logic ECLK
-);
-
-  if (FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK));
-  else begin
-    // *** BUG 
-    // VERY IMPORTANT.
-    // This part functionally models a clock gater, but does not necessarily meet the timing constrains a real standard cell would.
-    // Do not use this in synthesis!
-    logic   enable_q;
-    always_latch begin
-      if(~CLK) begin
-        enable_q <= E | SE;
-      end
-    end
-    assign ECLK = enable_q & CLK;
-  end    
-
-endmodule
diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv
index 437907e55..20d3cb8f6 100644
--- a/src/lsu/lrsc.sv
+++ b/src/lsu/lrsc.sv
@@ -45,7 +45,6 @@ module lrsc import cvw::*;  #(parameter cvw_t P) (
   localparam RESERVATION_SET_SIZE_IN_BYTES = P.XLEN/8;
   localparam RESERVATION_SET_ADDRESS_BITS = $clog2(RESERVATION_SET_SIZE_IN_BYTES); // 2 for rv32, 3 for rv64
 
-  // possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest.
   // Handle atomic load reserved / store conditional
   logic [P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS]        ReservationPAdrW;
   logic                        ReservationValidM, ReservationValidW;