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Changed names of lsu address signals.

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This commit is contained in:
Ross Thompson 2021-12-29 15:03:34 -06:00
parent 60f0339690
commit aa227ce97c
9 changed files with 63 additions and 64 deletions
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2
wally-pipelined/regression/linux-wave.do
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@ -342,7 +342,7 @@ add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/IEUAdrM add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/IEUAdrM
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/LsuPAdrM
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM

2
wally-pipelined/regression/wave.do
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@ -322,7 +322,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testb
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/LsuPAdrM
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM

10
wally-pipelined/src/cache/cachereplacementpolicy.sv vendored
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@ -29,7 +29,7 @@ module cachereplacementpolicy
(input logic clk, reset, (input logic clk, reset,
input logic [NUMWAYS-1:0] WayHit, input logic [NUMWAYS-1:0] WayHit,
output logic [NUMWAYS-1:0] VictimWay, output logic [NUMWAYS-1:0] VictimWay,
input logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] MemPAdrM, input logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] LsuPAdrM,
input logic [INDEXLEN-1:0] RAdr, input logic [INDEXLEN-1:0] RAdr,
input logic LRUWriteEn input logic LRUWriteEn
); );
@ -44,7 +44,7 @@ module cachereplacementpolicy
logic [NUMWAYS-2:0] NewReplacement; logic [NUMWAYS-2:0] NewReplacement;
logic [NUMWAYS-2:0] NewReplacementD; logic [NUMWAYS-2:0] NewReplacementD;
logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] MemPAdrMD; logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] LsuPAdrMD;
logic [INDEXLEN-1:0] RAdrD; logic [INDEXLEN-1:0] RAdrD;
logic LRUWriteEnD; logic LRUWriteEnD;
@ -52,18 +52,18 @@ module cachereplacementpolicy
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (reset) begin if (reset) begin
RAdrD <= '0; RAdrD <= '0;
MemPAdrMD <= '0; LsuPAdrMD <= '0;
LRUWriteEnD <= 0; LRUWriteEnD <= 0;
NewReplacementD <= '0; NewReplacementD <= '0;
for(int index = 0; index < NUMLINES; index++) for(int index = 0; index < NUMLINES; index++)
ReplacementBits[index] <= '0; ReplacementBits[index] <= '0;
end else begin end else begin
RAdrD <= RAdr; RAdrD <= RAdr;
MemPAdrMD <= MemPAdrM; LsuPAdrMD <= LsuPAdrM;
LRUWriteEnD <= LRUWriteEn; LRUWriteEnD <= LRUWriteEn;
NewReplacementD <= NewReplacement; NewReplacementD <= NewReplacement;
if (LRUWriteEnD) begin if (LRUWriteEnD) begin
ReplacementBits[MemPAdrMD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacementD; ReplacementBits[LsuPAdrMD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacementD;
end end
end end
end end

16
wally-pipelined/src/cache/dcache.sv vendored
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@ -37,7 +37,7 @@ module dcache
input logic [1:0] AtomicM, input logic [1:0] AtomicM,
input logic FlushDCacheM, input logic FlushDCacheM,
input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits.
input logic [`PA_BITS-1:0] MemPAdrM, // physical address input logic [`PA_BITS-1:0] LsuPAdrM, // physical address
input logic [`XLEN-1:0] FinalWriteDataM, input logic [`XLEN-1:0] FinalWriteDataM,
output logic [`XLEN-1:0] ReadDataWordM, output logic [`XLEN-1:0] ReadDataWordM,
@ -124,7 +124,7 @@ module dcache
mux3 #(INDEXLEN) mux3 #(INDEXLEN)
AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d1(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.d2(FlushAdr), .d2(FlushAdr),
.s(SelAdrM), .s(SelAdrM),
.y(RAdr)); .y(RAdr));
@ -134,7 +134,7 @@ module dcache
.reset, .reset,
.RAdr, .RAdr,
.WAdr(RAdr), // *** Reduce after addressing in icache also .WAdr(RAdr), // *** Reduce after addressing in icache also
.PAdr(MemPAdrM), .PAdr(LsuPAdrM),
.WriteEnable(SRAMWayWriteEnable), .WriteEnable(SRAMWayWriteEnable),
.VDWriteEnable(VDWriteEnableWay), .VDWriteEnable(VDWriteEnableWay),
.WriteWordEnable(SRAMWordEnable), .WriteWordEnable(SRAMWordEnable),
@ -160,7 +160,7 @@ module dcache
cachereplacementpolicy(.clk, .reset, cachereplacementpolicy(.clk, .reset,
.WayHit, .WayHit,
.VictimWay, .VictimWay,
.MemPAdrM(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .LsuPAdrM(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.RAdr, .RAdr,
.LRUWriteEn); .LRUWriteEn);
end else begin end else begin
@ -191,12 +191,12 @@ module dcache
// variable input mux // variable input mux
assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]]; assign ReadDataWordM = ReadDataBlockSetsM[LsuPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]];
// Write Path CPU (IEU) side // Write Path CPU (IEU) side
onehotdecoder #(LOGWPL) onehotdecoder #(LOGWPL)
adrdec(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), adrdec(.bin(LsuPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
.decoded(MemPAdrDecodedW)); .decoded(MemPAdrDecodedW));
assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW; assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW;
@ -216,8 +216,8 @@ module dcache
.y(SRAMWriteData)); .y(SRAMWriteData));
mux3 #(`PA_BITS) BaseAdrMux(.d0({MemPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), mux3 #(`PA_BITS) BaseAdrMux(.d0({LsuPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d1({VictimTag, LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
.s({SelFlush, SelEvict}), .s({SelFlush, SelEvict}),
.y(DCacheBusAdr)); .y(DCacheBusAdr));

2
wally-pipelined/src/cache/icache.sv vendored
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@ -165,7 +165,7 @@ module icache
cachereplacementpolicy(.clk, .reset, cachereplacementpolicy(.clk, .reset,
.WayHit, .WayHit,
.VictimWay, .VictimWay,
.MemPAdrM(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .LsuPAdrM(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.RAdr, .RAdr,
.LRUWriteEn); // *** connect .LRUWriteEn); // *** connect
end else begin end else begin

14
wally-pipelined/src/lsu/lrsc.sv
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@ -31,10 +31,10 @@ module lrsc
input logic clk, reset, input logic clk, reset,
input logic FlushW, CPUBusy, input logic FlushW, CPUBusy,
input logic MemReadM, input logic MemReadM,
input logic [1:0] LsuRWM, input logic [1:0] PreLsuRWM,
output logic [1:0] DCacheRWM, output logic [1:0] LsuRWM,
input logic [1:0] LsuAtomicM, input logic [1:0] LsuAtomicM,
input logic [`PA_BITS-1:0] MemPAdrM, // from mmu to dcache input logic [`PA_BITS-1:0] LsuPAdrM, // from mmu to dcache
output logic SquashSCW output logic SquashSCW
); );
// Handle atomic load reserved / store conditional // Handle atomic load reserved / store conditional
@ -44,16 +44,16 @@ module lrsc
logic SquashSCM; logic SquashSCM;
assign lrM = MemReadM && LsuAtomicM[0]; assign lrM = MemReadM && LsuAtomicM[0];
assign scM = LsuRWM[0] && LsuAtomicM[0]; assign scM = PreLsuRWM[0] && LsuAtomicM[0];
assign WriteAdrMatchM = LsuRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW; assign WriteAdrMatchM = PreLsuRWM[0] && (LsuPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
assign SquashSCM = scM && ~WriteAdrMatchM; assign SquashSCM = scM && ~WriteAdrMatchM;
assign DCacheRWM = SquashSCM ? 2'b00 : LsuRWM; assign LsuRWM = SquashSCM ? 2'b00 : PreLsuRWM;
always_comb begin // ReservationValidM (next value of valid reservation) always_comb begin // ReservationValidM (next value of valid reservation)
if (lrM) ReservationValidM = 1; // set valid on load reserve if (lrM) ReservationValidM = 1; // set valid on load reserve
else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc
else ReservationValidM = ReservationValidW; // otherwise don't change valid else ReservationValidM = ReservationValidW; // otherwise don't change valid
end end
flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, LsuPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW); flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW);
endmodule endmodule

62
wally-pipelined/src/lsu/lsu.sv
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@ -90,16 +90,16 @@ module lsu
logic DTLBPageFaultM; logic DTLBPageFaultM;
logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache logic [`PA_BITS-1:0] LsuPAdrM; // from mmu to dcache
logic [`XLEN+1:0] IEUAdrExtM; logic [`XLEN+1:0] IEUAdrExtM;
logic DTLBMissM; logic DTLBMissM;
logic DTLBWriteM; logic DTLBWriteM;
logic [1:0] DCacheRWM;
logic [1:0] LsuRWM; logic [1:0] LsuRWM;
logic [1:0] PreLsuRWM;
logic [2:0] LsuFunct3M; logic [2:0] LsuFunct3M;
logic [1:0] LsuAtomicM; logic [1:0] LsuAtomicM;
logic [`PA_BITS-1:0] LsuPAdrM, LocalLsuBusAdr; logic [`PA_BITS-1:0] PreLsuPAdrM, LocalLsuBusAdr;
logic [11:0] LsuAdrE, DCacheAdrE; logic [11:0] LsuAdrE, DCacheAdrE;
logic CPUBusy; logic CPUBusy;
logic MemReadM; logic MemReadM;
@ -210,11 +210,11 @@ module lsu
// arbiter between IEU and hptw // arbiter between IEU and hptw
// multiplex the outputs to LSU // multiplex the outputs to LSU
mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, LsuRWM); mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLsuRWM);
mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M); mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M);
mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM); mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM);
mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, LsuAdrE); mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, LsuAdrE);
mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, LsuPAdrM); mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLsuPAdrM);
assign CPUBusy = StallW & ~SelHPTW; assign CPUBusy = StallW & ~SelHPTW;
@ -224,16 +224,16 @@ module lsu
// turns out because we cannot pipeline hptw requests we don't need this register // turns out because we cannot pipeline hptw requests we don't need this register
//flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle
//assign LsuRWM = SelHPTW ? {HPTWRead, 1'b0} : MemRWM; //assign PreLsuRWM = SelHPTW ? {HPTWRead, 1'b0} : MemRWM;
//assign LsuAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0]; //assign LsuAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0];
//assign LsuAtomicM = SelHPTW ? 2'b00 : AtomicM; //assign LsuAtomicM = SelHPTW ? 2'b00 : AtomicM;
//assign LsuPAdrM = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0]; //assign PreLsuPAdrM = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0];
// Specify which type of page fault is occurring // Specify which type of page fault is occurring
// *** `MEM_VIRTMEM // *** `MEM_VIRTMEM
assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1]; assign DTLBLoadPageFaultM = DTLBPageFaultM & PreLsuRWM[1];
assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0]; assign DTLBStorePageFaultM = DTLBPageFaultM & PreLsuRWM[0];
assign DCacheAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE; assign DCacheAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE;
@ -250,11 +250,11 @@ module lsu
assign DTLBWriteM = 1'b0; assign DTLBWriteM = 1'b0;
assign ITLBWriteF = 1'b0; assign ITLBWriteF = 1'b0;
assign LsuRWM = MemRWM; assign PreLsuRWM = MemRWM;
assign LsuFunct3M = Funct3M; assign LsuFunct3M = Funct3M;
assign LsuAtomicM = AtomicM; assign LsuAtomicM = AtomicM;
assign LsuAdrE = IEUAdrE[11:0]; assign LsuAdrE = IEUAdrE[11:0];
assign LsuPAdrM = IEUAdrExtM; assign PreLsuPAdrM = IEUAdrExtM;
assign CPUBusy = StallW; assign CPUBusy = StallW;
assign DTLBLoadPageFaultM = 1'b0; assign DTLBLoadPageFaultM = 1'b0;
@ -272,21 +272,21 @@ module lsu
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .DisableTranslation(SelHPTW), .PrivilegeModeW, .DisableTranslation(SelHPTW),
.PAdr(LsuPAdrM), .PAdr(PreLsuPAdrM),
.VAdr(IEUAdrM), .VAdr(IEUAdrM),
.Size(LsuFunct3M[1:0]), .Size(LsuFunct3M[1:0]),
.PTE, .PTE,
.PageTypeWriteVal(PageType), .PageTypeWriteVal(PageType),
.TLBWrite(DTLBWriteM), .TLBWrite(DTLBWriteM),
.TLBFlush(DTLBFlushM), .TLBFlush(DTLBFlushM),
.PhysicalAddress(MemPAdrM), .PhysicalAddress(LsuPAdrM),
.TLBMiss(DTLBMissM), .TLBMiss(DTLBMissM),
.Cacheable(CacheableM), .Cacheable(CacheableM),
.Idempotent(), .AtomicAllowed(), .Idempotent(), .AtomicAllowed(),
.TLBPageFault(DTLBPageFaultM), .TLBPageFault(DTLBPageFaultM),
.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM, .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM,
.AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), /// atomicaccessm is probably a bug .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), /// atomicaccessm is probably a bug
.WriteAccessM(LsuRWM[0]), .ReadAccessM(LsuRWM[1]), .WriteAccessM(PreLsuRWM[0]), .ReadAccessM(PreLsuRWM[1]),
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist? ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
@ -305,7 +305,7 @@ module lsu
assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0]; assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0];
end else begin end else begin
assign MemPAdrM = LsuPAdrM; assign LsuPAdrM = PreLsuPAdrM;
assign DTLBMissM = 0; assign DTLBMissM = 0;
assign CacheableM = 1; assign CacheableM = 1;
assign DTLBPageFaultM = 0; assign DTLBPageFaultM = 0;
@ -323,12 +323,12 @@ module lsu
// use PreLsu as prefix for lrsc // use PreLsu as prefix for lrsc
generate generate
if (`A_SUPPORTED) begin if (`A_SUPPORTED) begin
assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; assign MemReadM = PreLsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM, lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLsuRWM, .LsuAtomicM, .LsuPAdrM,
.SquashSCW, .DCacheRWM); .SquashSCW, .LsuRWM);
end else begin end else begin
assign SquashSCW = 0; assign SquashSCW = 0;
assign DCacheRWM = LsuRWM; assign LsuRWM = PreLsuRWM;
end end
endgenerate endgenerate
@ -381,12 +381,12 @@ module lsu
dcache dcache(.clk, .reset, .CPUBusy, dcache dcache(.clk, .reset, .CPUBusy,
.MemRWM(DCacheRWM), .MemRWM(LsuRWM),
.Funct3M(LsuFunct3M), .Funct3M(LsuFunct3M),
.Funct7M, .FlushDCacheM, .Funct7M, .FlushDCacheM,
.AtomicM(LsuAtomicM), .AtomicM(LsuAtomicM),
.MemAdrE(DCacheAdrE), .MemAdrE(DCacheAdrE),
.MemPAdrM, .LsuPAdrM,
.FinalWriteDataM, .ReadDataWordM, .DCacheStall, .FinalWriteDataM, .ReadDataWordM, .DCacheStall,
.DCacheMiss, .DCacheAccess, .IgnoreRequest, .DCacheMiss, .DCacheAccess, .IgnoreRequest,
.CacheableM(CacheableM), .CacheableM(CacheableM),
@ -408,7 +408,7 @@ module lsu
// finally swr // finally swr
subwordread subwordread(.ReadDataWordMuxM, subwordread subwordread(.ReadDataWordMuxM,
.MemPAdrM(MemPAdrM[2:0]), .LsuPAdrM(LsuPAdrM[2:0]),
.Funct3M(LsuFunct3M), .Funct3M(LsuFunct3M),
.ReadDataM); .ReadDataM);
@ -423,7 +423,7 @@ module lsu
endgenerate endgenerate
subwordwrite subwordwrite(.HRDATA(ReadDataWordM), subwordwrite subwordwrite(.HRDATA(ReadDataWordM),
.HADDRD(MemPAdrM[2:0]), .HADDRD(LsuPAdrM[2:0]),
.HSIZED({LsuFunct3M[2], 1'b0, LsuFunct3M[1:0]}), .HSIZED({LsuFunct3M[2], 1'b0, LsuFunct3M[1:0]}),
.HWDATAIN(FinalAMOWriteDataM), .HWDATAIN(FinalAMOWriteDataM),
.HWDATA(FinalWriteDataM)); .HWDATA(FinalWriteDataM));
@ -452,8 +452,8 @@ module lsu
//assign LocalLsuBusAdr = SelUncachedAdr ? MemPAdrM : {DCacheBusAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}} ; //assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : {DCacheBusAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}} ;
assign LocalLsuBusAdr = SelUncachedAdr ? MemPAdrM : DCacheBusAdr ; assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : DCacheBusAdr ;
assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLsuBusAdr; assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLsuBusAdr;
@ -491,8 +491,8 @@ module lsu
case(BusCurrState) case(BusCurrState)
STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY;
else if(DCacheRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE; else if(LsuRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE;
else if(DCacheRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ; else if(LsuRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ;
else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH; else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH;
else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE; else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE;
STATE_BUS_UNCACHED_WRITE: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; STATE_BUS_UNCACHED_WRITE: if(LsuBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE;
@ -514,24 +514,24 @@ module lsu
assign CntReset = BusCurrState == STATE_BUS_READY; assign CntReset = BusCurrState == STATE_BUS_READY;
assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|DCacheRWM)) | DCacheFetchLine | DCacheWriteLine)) | assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|LsuRWM)) | DCacheFetchLine | DCacheWriteLine)) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) |
(BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_UNCACHED_READ) |
(BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_FETCH) |
(BusCurrState == STATE_BUS_WRITE); (BusCurrState == STATE_BUS_WRITE);
assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE; assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE;
assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (DCacheRWM[0])) | assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (LsuRWM[0])) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE); (BusCurrState == STATE_BUS_UNCACHED_WRITE);
assign LsuBusWrite = UnCachedLsuBusWrite | (BusCurrState == STATE_BUS_WRITE); assign LsuBusWrite = UnCachedLsuBusWrite | (BusCurrState == STATE_BUS_WRITE);
assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|DCacheRWM[1])) | assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|LsuRWM[1])) |
(BusCurrState == STATE_BUS_UNCACHED_READ); (BusCurrState == STATE_BUS_UNCACHED_READ);
assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH); assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH);
assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) | assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) |
(BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck); (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck);
assign BusCommittedM = BusCurrState != STATE_BUS_READY; assign BusCommittedM = BusCurrState != STATE_BUS_READY;
assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|DCacheRWM & ~CacheableM)) | assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LsuRWM & ~CacheableM)) |
(BusCurrState == STATE_BUS_UNCACHED_READ | (BusCurrState == STATE_BUS_UNCACHED_READ |
BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_UNCACHED_READ_DONE |
BusCurrState == STATE_BUS_UNCACHED_WRITE | BusCurrState == STATE_BUS_UNCACHED_WRITE |

12
wally-pipelined/src/lsu/subwordread.sv
View File

@ -28,7 +28,7 @@
module subwordread module subwordread
( (
input logic [`XLEN-1:0] ReadDataWordMuxM, input logic [`XLEN-1:0] ReadDataWordMuxM,
input logic [2:0] MemPAdrM, input logic [2:0] LsuPAdrM,
input logic [2:0] Funct3M, input logic [2:0] Funct3M,
output logic [`XLEN-1:0] ReadDataM output logic [`XLEN-1:0] ReadDataM
); );
@ -42,7 +42,7 @@ module subwordread
if (`XLEN == 64) begin if (`XLEN == 64) begin
// ByteMe mux // ByteMe mux
always_comb always_comb
case(MemPAdrM[2:0]) case(LsuPAdrM[2:0])
3'b000: ByteM = ReadDataWordMuxM[7:0]; 3'b000: ByteM = ReadDataWordMuxM[7:0];
3'b001: ByteM = ReadDataWordMuxM[15:8]; 3'b001: ByteM = ReadDataWordMuxM[15:8];
3'b010: ByteM = ReadDataWordMuxM[23:16]; 3'b010: ByteM = ReadDataWordMuxM[23:16];
@ -55,7 +55,7 @@ module subwordread
// halfword mux // halfword mux
always_comb always_comb
case(MemPAdrM[2:1]) case(LsuPAdrM[2:1])
2'b00: HalfwordM = ReadDataWordMuxM[15:0]; 2'b00: HalfwordM = ReadDataWordMuxM[15:0];
2'b01: HalfwordM = ReadDataWordMuxM[31:16]; 2'b01: HalfwordM = ReadDataWordMuxM[31:16];
2'b10: HalfwordM = ReadDataWordMuxM[47:32]; 2'b10: HalfwordM = ReadDataWordMuxM[47:32];
@ -65,7 +65,7 @@ module subwordread
logic [31:0] WordM; logic [31:0] WordM;
always_comb always_comb
case(MemPAdrM[2]) case(LsuPAdrM[2])
1'b0: WordM = ReadDataWordMuxM[31:0]; 1'b0: WordM = ReadDataWordMuxM[31:0];
1'b1: WordM = ReadDataWordMuxM[63:32]; 1'b1: WordM = ReadDataWordMuxM[63:32];
endcase endcase
@ -85,7 +85,7 @@ module subwordread
end else begin // 32-bit end else begin // 32-bit
// byte mux // byte mux
always_comb always_comb
case(MemPAdrM[1:0]) case(LsuPAdrM[1:0])
2'b00: ByteM = ReadDataWordMuxM[7:0]; 2'b00: ByteM = ReadDataWordMuxM[7:0];
2'b01: ByteM = ReadDataWordMuxM[15:8]; 2'b01: ByteM = ReadDataWordMuxM[15:8];
2'b10: ByteM = ReadDataWordMuxM[23:16]; 2'b10: ByteM = ReadDataWordMuxM[23:16];
@ -94,7 +94,7 @@ module subwordread
// halfword mux // halfword mux
always_comb always_comb
case(MemPAdrM[1]) case(LsuPAdrM[1])
1'b0: HalfwordM = ReadDataWordMuxM[15:0]; 1'b0: HalfwordM = ReadDataWordMuxM[15:0];
1'b1: HalfwordM = ReadDataWordMuxM[31:16]; 1'b1: HalfwordM = ReadDataWordMuxM[31:16];
endcase endcase

7
wally-pipelined/testbench/testbench-linux.sv
View File

@ -49,6 +49,7 @@ module testbench();
////////////////////////////////// HARDWARE /////////////////////////////////// ////////////////////////////////// HARDWARE ///////////////////////////////////
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
logic clk, reset_ext; logic clk, reset_ext;
logic reset;
initial begin reset_ext <= 1; # 22; reset_ext <= 0; end initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
always begin clk <= 1; # 5; clk <= 0; # 5; end always begin clk <= 1; # 5; clk <= 0; # 5; end
@ -77,7 +78,7 @@ module testbench();
assign GPIOPinsIn = 0; assign GPIOPinsIn = 0;
assign UARTSin = 1; assign UARTSin = 1;
wallypipelinedsoc dut(.clk, .reset_ext, wallypipelinedsoc dut(.clk, .reset, .reset_ext,
.HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK,
.HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HTRANS, .HMASTLOCK,
@ -85,8 +86,6 @@ module testbench();
.UARTSin, .UARTSout, .UARTSin, .UARTSout,
.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn); .SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
logic reset;
assign reset = dut.reset;
// Write Back stage signals not needed by Wally itself // Write Back stage signals not needed by Wally itself
parameter nop = 'h13; parameter nop = 'h13;
@ -446,7 +445,7 @@ module testbench();
end \ end \
if(`"STAGE`"=="M") begin \ if(`"STAGE`"=="M") begin \
// override on special conditions \ // override on special conditions \
if (dut.hart.lsu.MemPAdrM == 'h10000005) \ if (dut.hart.lsu.LsuPAdrM == 'h10000005) \
//$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, InstrCountW-1); \ //$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, InstrCountW-1); \
force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
else \ else \