mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge pull request #615 from ross144/main
Updates for branch predictor configs and nightly regression. Correctly automaticed this time.
This commit is contained in:
David Harris
GitHub
commit
aa1fe30aae
@ -285,27 +285,30 @@ RAS_SIZE 32'd4
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deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc
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RAS_SIZE 32'd6
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deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
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deriv bpred_GSHARE_10_10_10_1_rv32gc rv32gc
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RAS_SIZE 32'd10
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deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
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RAS_SIZE 32'd16
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deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc
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deriv bpred_GSHARE_10_16_6_1_rv32gc rv32gc
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BTB_SIZE 32'd6
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deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc
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deriv bpred_GSHARE_10_16_8_1_rv32gc rv32gc
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BTB_SIZE 32'd8
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deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc
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deriv bpred_GSHARE_10_16_12_1_rv32gc rv32gc
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BTB_SIZE 32'd12
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deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc
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deriv bpred_GSHARE_10_16_14_1_rv32gc rv32gc
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BTB_SIZE 32'd14
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deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc
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deriv bpred_GSHARE_10_16_16_1_rv32gc rv32gc
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BTB_SIZE 32'd16
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deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc
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INSTR_CLASS_PRED 0
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@ -354,25 +357,25 @@ INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_6_10_0_rv32gc rv32gc bpred_GSHARE_10_6_10_1_rv32gc
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc
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deriv bpred_GSHARE_10_10_10_0_rv32gc rv32gc bpred_GSHARE_10_10_10_1_rv32gc
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_2_6_0_rv32gc rv32gc bpred_GSHARE_10_2_6_1_rv32gc
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deriv bpred_GSHARE_10_16_6_0_rv32gc rv32gc bpred_GSHARE_10_16_6_1_rv32gc
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_2_8_0_rv32gc rv32gc bpred_GSHARE_10_2_8_1_rv32gc
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deriv bpred_GSHARE_10_16_8_0_rv32gc rv32gc bpred_GSHARE_10_16_8_1_rv32gc
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_2_12_0_rv32gc rv32gc bpred_GSHARE_10_2_12_1_rv32gc
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deriv bpred_GSHARE_10_16_12_0_rv32gc rv32gc bpred_GSHARE_10_16_12_1_rv32gc
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_2_14_0_rv32gc rv32gc bpred_GSHARE_10_2_14_1_rv32gc
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deriv bpred_GSHARE_10_16_14_0_rv32gc rv32gc bpred_GSHARE_10_16_14_1_rv32gc
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INSTR_CLASS_PRED 0
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deriv bpred_GSHARE_10_2_16_0_rv32gc rv32gc bpred_GSHARE_10_2_16_1_rv32gc
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deriv bpred_GSHARE_10_16_16_0_rv32gc rv32gc bpred_GSHARE_10_16_16_1_rv32gc
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INSTR_CLASS_PRED 0
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# Cache configurations
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@ -1,12 +1,12 @@
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../logs/rv32gc_gshare6.log gshare 6
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../logs/rv32gc_gshare8.log gshare 8
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../logs/rv32gc_gshare10.log gshare 10
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../logs/rv32gc_gshare12.log gshare 12
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../logs/rv32gc_gshare14.log gshare 14
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../logs/rv32gc_gshare16.log gshare 16
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../logs/rv32gc_twobit6.log twobit 6
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../logs/rv32gc_twobit8.log twobit 8
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../logs/rv32gc_twobit10.log twobit 10
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../logs/rv32gc_twobit12.log twobit 12
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../logs/rv32gc_twobit14.log twobit 14
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../logs/rv32gc_twobit16.log twobit 16
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../logs/bpred_GSHARE_6_16_10_0_rv32gc_embench.log gshare 6
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../logs/bpred_GSHARE_8_16_10_0_rv32gc_embench.log gshare 8
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../logs/bpred_GSHARE_10_16_10_0_rv32gc_embench.log gshare 10
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../logs/bpred_GSHARE_12_16_10_0_rv32gc_embench.log gshare 12
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../logs/bpred_GSHARE_14_16_10_0_rv32gc_embench.log gshare 14
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../logs/bpred_GSHARE_16_16_10_0_rv32gc_embench.log gshare 16
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../logs/bpred_TWOBIT_6_16_10_0_rv32gc_embench.log twobit 6
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../logs/bpred_TWOBIT_8_16_10_0_rv32gc_embench.log twobit 8
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../logs/bpred_TWOBIT_10_16_10_0_rv32gc_embench.log twobit 10
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../logs/bpred_TWOBIT_12_16_10_0_rv32gc_embench.log twobit 12
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../logs/bpred_TWOBIT_14_16_10_0_rv32gc_embench.log twobit 14
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../logs/bpred_TWOBIT_16_16_10_0_rv32gc_embench.log twobit 16
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@ -1,6 +1,6 @@
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../logs/rv32gc_BTB6.log btb 6
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../logs/rv32gc_BTB8.log btb 8
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../logs/rv32gc_BTB10.log btb 10
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../logs/rv32gc_BTB12.log btb 12
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../logs/rv32gc_BTB14.log btb 14
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../logs/rv32gc_BTB16.log btb 16
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../logs/bpred_GSHARE_16_16_6_0_rv32gc_embench.log btb 6
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../logs/bpred_GSHARE_16_16_8_0_rv32gc_embench.log btb 8
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../logs/bpred_GSHARE_16_16_10_0_rv32gc_embench.log btb 10
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../logs/bpred_GSHARE_16_16_12_0_rv32gc_embench.log btb 12
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../logs/bpred_GSHARE_16_16_14_0_rv32gc_embench.log btb 14
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../logs/bpred_GSHARE_16_16_16_0_rv32gc_embench.log btb 16
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@ -1,6 +1,6 @@
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../logs/rv32gc_class6.log class 6
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../logs/rv32gc_class8.log class 8
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../logs/rv32gc_class10.log class 10
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../logs/rv32gc_class12.log class 12
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../logs/rv32gc_class14.log class 14
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../logs/rv32gc_class16.log class 16
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../logs/bpred_GSHARE_16_16_6_1_rv32gc_embench.log btb 6
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../logs/bpred_GSHARE_16_16_8_1_rv32gc_embench.log btb 8
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../logs/bpred_GSHARE_16_16_10_1_rv32gc_embench.log btb 10
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../logs/bpred_GSHARE_16_16_12_1_rv32gc_embench.log btb 12
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../logs/bpred_GSHARE_16_16_14_1_rv32gc_embench.log btb 14
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../logs/bpred_GSHARE_16_16_16_1_rv32gc_embench.log btb 16
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@ -1,5 +1,5 @@
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../logs/rv32gc_RAS3.log ras 3
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../logs/rv32gc_RAS4.log ras 4
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../logs/rv32gc_RAS6.log ras 6
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../logs/rv32gc_RAS10.log ras 10
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../logs/rv32gc_RAS16.log ras 16
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../logs/bpred_GSHARE_10_3_10_0_rv32gc_embench.log ras 3
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../logs/bpred_GSHARE_10_4_10_0_rv32gc_embench.log ras 4
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../logs/bpred_GSHARE_10_6_10_0_rv32gc_embench.log ras 6
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../logs/bpred_GSHARE_10_10_10_0_rv32gc_embench.log ras 10
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../logs/bpred_GSHARE_10_16_10_0_rv32gc_embench.log ras 16
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@ -11,6 +11,9 @@
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#
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##################################
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import sys,os,shutil
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import multiprocessing
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class bcolors:
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HEADER = '\033[95m'
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@ -215,6 +218,55 @@ if (nightly):
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["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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### branch predictor simulation
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["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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# btb
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["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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# ras
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["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
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# enable floating-point tests when lint is fixed
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# ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
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# ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],
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@ -232,11 +284,17 @@ if (nightly):
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for test in derivconfigtests:
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config = test[0];
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tests = test[1];
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if(len(test) >= 4 and test[2] == "configOptions"):
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configOptions = test[3]
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cmdPrefix = "vsim > {} -c <<!\ndo wally-batch.do "+config+" configOptions"
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else:
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configOptions = ""
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cmdPrefix = "vsim > {} -c <<!\ndo wally-batch.do "+config
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for t in tests:
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tc = TestCase(
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name=t,
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variant=config,
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cmd="vsim > {} -c <<!\ndo wally-batch.do "+config+" "+t+"\n!",
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cmd=cmdPrefix+" "+t+" "+configOptions+"\n!",
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grepstr="All tests ran without failures")
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configs.append(tc)
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@ -306,13 +364,16 @@ def main():
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# Also it is slow to run.
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# configs.append(getBuildrootTC(boot=False))
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os.system('rm -f cov/*.ucdb')
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elif '-nightly' in sys.argv:
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TIMEOUT_DUR = 60*1440 # 1 day
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configs.append(getBuildrootTC(boot=False))
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else:
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TIMEOUT_DUR = 10*60 # seconds
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configs.append(getBuildrootTC(boot=False))
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# Scale the number of concurrent processes to the number of test cases, but
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# max out at a limited number of concurrent processes to not overwhelm the system
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with Pool(processes=min(len(configs),40)) as pool:
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with Pool(processes=min(len(configs),multiprocessing.cpu_count())) as pool:
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num_fail = 0
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results = {}
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for config in configs:
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@ -89,10 +89,10 @@ if {$2 eq "buildroot"} {
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# **** fix this so we can pass any number of +defines.
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# only allows 3 right now
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vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 $5 $6 $7
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vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$4 -o testbenchopt
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vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$3 ${4} -o testbenchopt
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vsim -lib wkdir/work_${1}_${3}_${4} testbenchopt -fatal 7 -suppress 3829
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# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time
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#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
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@ -88,15 +88,17 @@ module bpred import cvw::*; #(parameter cvw_t P) (
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logic [P.XLEN-1:0] BPBTAD;
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logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF;
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logic BPBranchF, BPJumpF, BPReturnF, BPCallF;
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logic BPBranchD, BPJumpD, BPReturnD, BPCallD;
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logic ReturnD, CallD;
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logic ReturnE, CallE;
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logic BranchM, JumpM, ReturnM, CallM;
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logic BranchW, JumpW, ReturnW, CallW;
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logic BPReturnWrongD;
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logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF;
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logic BPBranchF, BPJumpF, BPReturnF, BPCallF;
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logic BPBranchD, BPJumpD, BPReturnD, BPCallD;
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logic ReturnD, CallD;
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logic ReturnE, CallE;
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logic BranchM, JumpM, ReturnM, CallM;
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logic BranchW, JumpW, ReturnW, CallW;
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logic BPReturnWrongD;
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logic [P.XLEN-1:0] BPBTAE;
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logic BPBTAWrongM;
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logic PCSrcM;
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// Part 1 branch direction prediction
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if (P.BPRED_TYPE == `BP_TWOBIT) begin:Predictor
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@ -144,6 +146,8 @@ module bpred import cvw::*; #(parameter cvw_t P) (
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.BranchD, .BranchE, .BranchM, .PCSrcE);
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end
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flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
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// Part 2 Branch target address prediction
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// BTB contains target address for all CFI
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@ -152,6 +156,7 @@ module bpred import cvw::*; #(parameter cvw_t P) (
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.PCNextF, .PCF, .PCD, .PCE, .PCM,
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.BPBTAF, .BPBTAD, .BPBTAE,
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.BTBIClassF({BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF}),
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.BPBTAWrongM,
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.IClassWrongM, .IClassWrongE,
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.IEUAdrE, .IEUAdrM,
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.InstrClassD({CallD, ReturnD, JumpD, BranchD}),
|
||||
@ -196,7 +201,7 @@ module bpred import cvw::*; #(parameter cvw_t P) (
|
||||
|
||||
if(P.ZIHPM_SUPPORTED) begin
|
||||
logic [P.XLEN-1:0] RASPCD, RASPCE;
|
||||
logic BTAWrongE, RASPredPCWrongE;
|
||||
logic RASPredPCWrongE;
|
||||
// performance counters
|
||||
// 1. class (class wrong / minstret) (IClassWrongM / csr) // Correct now
|
||||
// 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal)
|
||||
@ -208,14 +213,15 @@ module bpred import cvw::*; #(parameter cvw_t P) (
|
||||
// By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
|
||||
// both without the above inaccuracies.
|
||||
// **** use BPBTAWrongM from BTB.
|
||||
assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE;
|
||||
assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE;
|
||||
|
||||
flopenrc #(P.XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
|
||||
flopenrc #(P.XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
|
||||
flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM,
|
||||
{BPDirPredWrongE, BTAWrongE, RASPredPCWrongE},
|
||||
{BPDirPredWrongM, BTAWrongM, RASPredPCWrongM});
|
||||
flopenrc #(2) BPPredWrongRegM(clk, reset, FlushM, ~StallM,
|
||||
{BPDirPredWrongE, RASPredPCWrongE},
|
||||
{BPDirPredWrongM, RASPredPCWrongM});
|
||||
|
||||
assign BTAWrongM = BPBTAWrongM & PCSrcM;
|
||||
|
||||
end else begin
|
||||
assign {BTAWrongM, RASPredPCWrongM} = '0;
|
||||
|
||||
@ -39,6 +39,7 @@ module btb import cvw::*; #(parameter cvw_t P,
|
||||
output logic [P.XLEN-1:0] BPBTAD,
|
||||
output logic [P.XLEN-1:0] BPBTAE,
|
||||
output logic [3:0] BTBIClassF, // BTB's guess at instruction class
|
||||
output logic BPBTAWrongM,
|
||||
// update
|
||||
input logic IClassWrongM, // BTB's instruction class guess was wrong
|
||||
input logic IClassWrongE,
|
||||
@ -57,7 +58,7 @@ module btb import cvw::*; #(parameter cvw_t P,
|
||||
logic [P.XLEN-1:0] IEUAdrW;
|
||||
logic [P.XLEN-1:0] PCW;
|
||||
logic BTBWrongE, BPBTAWrongE;
|
||||
logic BTBWrongM, BPBTAWrongM;
|
||||
logic BTBWrongM;
|
||||
|
||||
|
||||
// hashing function for indexing the PC
|
||||
|
||||
Loading…
Reference in New Issue
Block a user