From eccb7b7f49dc73ec1861c3f272615ab8161b2a16 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 1 Feb 2024 15:35:44 -0600 Subject: [PATCH 1/8] added branch predictor configs with embench to nightly. --- sim/regression-wally | 50 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/sim/regression-wally b/sim/regression-wally index 5f4e68bf1..3864d3b3e 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -11,6 +11,9 @@ # ################################## import sys,os,shutil +import multiprocessing + + class bcolors: HEADER = '\033[95m' @@ -215,6 +218,51 @@ if (nightly): ["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], ["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ### branch predictor simulation + + ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"]], + ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"]], + ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"]], + ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"]], + ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"]], + ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"]], + ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"]], + ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"]], + ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"]], + ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"]], + ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"]], + ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"]], + ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"]], + ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"]], + ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"]], + ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"]], + ["bpred_GSHARE_10_2_12_0_rv32gc", ["embench"]], + ["bpred_GSHARE_10_2_12_1_rv32gc", ["embench"]], + ["bpred_GSHARE_10_2_14_0_rv32gc", ["embench"]], + ["bpred_GSHARE_10_2_14_1_rv32gc", ["embench"]], + ["bpred_GSHARE_10_2_16_0_rv32gc", ["embench"]], + ["bpred_GSHARE_10_2_16_1_rv32gc", ["embench"]], + ["bpred_GSHARE_10_2_6_0_rv32gc", ["embench"]], + ["bpred_GSHARE_10_2_6_1_rv32gc", ["embench"]], + ["bpred_GSHARE_10_2_8_0_rv32gc", ["embench"]], + ["bpred_GSHARE_10_2_8_1_rv32gc", ["embench"]], + ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"]], + ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"]], + ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"]], + ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"]], + ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"]], + ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"]], + ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"]], + ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"]], + ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"]], + ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"]], + ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"]], + ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"]], + ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"]], + ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"]], + ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"]], + ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"]], + # enable floating-point tests when lint is fixed # ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]], # ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]], @@ -312,7 +360,7 @@ def main(): # Scale the number of concurrent processes to the number of test cases, but # max out at a limited number of concurrent processes to not overwhelm the system - with Pool(processes=min(len(configs),40)) as pool: + with Pool(processes=min(len(configs),multiprocessing.cpu_count())) as pool: num_fail = 0 results = {} for config in configs: From 5f0f8c2d3a0dfd48d10bfa9bcd7364eeb519c579 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 1 Feb 2024 16:42:25 -0600 Subject: [PATCH 2/8] Increased timeout for nighly regressions. --- sim/regression-wally | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sim/regression-wally b/sim/regression-wally index 3864d3b3e..67159eb1d 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -354,6 +354,9 @@ def main(): # Also it is slow to run. # configs.append(getBuildrootTC(boot=False)) os.system('rm -f cov/*.ucdb') + elif '-nightly' in sys.argv: + TIMEOUT_DUR = 60*1440 # 1 day + configs.append(getBuildrootTC(boot=False)) else: TIMEOUT_DUR = 10*60 # seconds configs.append(getBuildrootTC(boot=False)) From bd06a5ff88738322365f8fada48c28a6bb10c044 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 1 Feb 2024 16:57:33 -0600 Subject: [PATCH 3/8] Rough draft removal of duplicate BPBTAWrongE logic. --- src/ifu/bpred/bpred.sv | 32 +++++++++++++++++++------------- src/ifu/bpred/btb.sv | 3 ++- 2 files changed, 21 insertions(+), 14 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index faf537d91..006a60b1d 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -88,15 +88,17 @@ module bpred import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] BPBTAD; - logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF; - logic BPBranchF, BPJumpF, BPReturnF, BPCallF; - logic BPBranchD, BPJumpD, BPReturnD, BPCallD; - logic ReturnD, CallD; - logic ReturnE, CallE; - logic BranchM, JumpM, ReturnM, CallM; - logic BranchW, JumpW, ReturnW, CallW; - logic BPReturnWrongD; + logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF; + logic BPBranchF, BPJumpF, BPReturnF, BPCallF; + logic BPBranchD, BPJumpD, BPReturnD, BPCallD; + logic ReturnD, CallD; + logic ReturnE, CallE; + logic BranchM, JumpM, ReturnM, CallM; + logic BranchW, JumpW, ReturnW, CallW; + logic BPReturnWrongD; logic [P.XLEN-1:0] BPBTAE; + logic BPBTAWrongM; + logic PCSrcM; // Part 1 branch direction prediction if (P.BPRED_TYPE == `BP_TWOBIT) begin:Predictor @@ -144,6 +146,8 @@ module bpred import cvw::*; #(parameter cvw_t P) ( .BranchD, .BranchE, .BranchM, .PCSrcE); end + flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); + // Part 2 Branch target address prediction // BTB contains target address for all CFI @@ -152,6 +156,7 @@ module bpred import cvw::*; #(parameter cvw_t P) ( .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPBTAF, .BPBTAD, .BPBTAE, .BTBIClassF({BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF}), + .BPBTAWrongM, .IClassWrongM, .IClassWrongE, .IEUAdrE, .IEUAdrM, .InstrClassD({CallD, ReturnD, JumpD, BranchD}), @@ -196,7 +201,7 @@ module bpred import cvw::*; #(parameter cvw_t P) ( if(P.ZIHPM_SUPPORTED) begin logic [P.XLEN-1:0] RASPCD, RASPCE; - logic BTAWrongE, RASPredPCWrongE; + logic RASPredPCWrongE; // performance counters // 1. class (class wrong / minstret) (IClassWrongM / csr) // Correct now // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) @@ -208,14 +213,15 @@ module bpred import cvw::*; #(parameter cvw_t P) ( // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // both without the above inaccuracies. // **** use BPBTAWrongM from BTB. - assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE; assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE; flopenrc #(P.XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); flopenrc #(P.XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); - flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM, - {BPDirPredWrongE, BTAWrongE, RASPredPCWrongE}, - {BPDirPredWrongM, BTAWrongM, RASPredPCWrongM}); + flopenrc #(2) BPPredWrongRegM(clk, reset, FlushM, ~StallM, + {BPDirPredWrongE, RASPredPCWrongE}, + {BPDirPredWrongM, RASPredPCWrongM}); + + assign BTAWrongM = BPBTAWrongM & PCSrcM; end else begin assign {BTAWrongM, RASPredPCWrongM} = '0; diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 2d0d30727..448be38d0 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -39,6 +39,7 @@ module btb import cvw::*; #(parameter cvw_t P, output logic [P.XLEN-1:0] BPBTAD, output logic [P.XLEN-1:0] BPBTAE, output logic [3:0] BTBIClassF, // BTB's guess at instruction class + output logic BPBTAWrongM, // update input logic IClassWrongM, // BTB's instruction class guess was wrong input logic IClassWrongE, @@ -57,7 +58,7 @@ module btb import cvw::*; #(parameter cvw_t P, logic [P.XLEN-1:0] IEUAdrW; logic [P.XLEN-1:0] PCW; logic BTBWrongE, BPBTAWrongE; - logic BTBWrongM, BPBTAWrongM; + logic BTBWrongM; // hashing function for indexing the PC From f5afec9bf562288d0c0186ee6f63bb2727ed7ba7 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 1 Feb 2024 17:15:02 -0600 Subject: [PATCH 4/8] Fixed bugs in the regression-wally script required for branch predictor sweeps. --- sim/regression-wally | 88 ++++++++++++++++++++++---------------------- 1 file changed, 45 insertions(+), 43 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index 67159eb1d..7c389be70 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -220,48 +220,48 @@ if (nightly): ### branch predictor simulation - ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"]], - ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"]], - ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"]], - ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"]], - ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"]], - ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"]], - ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"]], - ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"]], - ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"]], - ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"]], - ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"]], - ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"]], - ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"]], - ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"]], - ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"]], - ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"]], - ["bpred_GSHARE_10_2_12_0_rv32gc", ["embench"]], - ["bpred_GSHARE_10_2_12_1_rv32gc", ["embench"]], - ["bpred_GSHARE_10_2_14_0_rv32gc", ["embench"]], - ["bpred_GSHARE_10_2_14_1_rv32gc", ["embench"]], - ["bpred_GSHARE_10_2_16_0_rv32gc", ["embench"]], - ["bpred_GSHARE_10_2_16_1_rv32gc", ["embench"]], - ["bpred_GSHARE_10_2_6_0_rv32gc", ["embench"]], - ["bpred_GSHARE_10_2_6_1_rv32gc", ["embench"]], - ["bpred_GSHARE_10_2_8_0_rv32gc", ["embench"]], - ["bpred_GSHARE_10_2_8_1_rv32gc", ["embench"]], - ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"]], - ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"]], - ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"]], - ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"]], - ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"]], - ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"]], - ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"]], - ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"]], - ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"]], - ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"]], - ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"]], - ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"]], - ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"]], - ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"]], - ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"]], - ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"]], + ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_12_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_12_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_14_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_14_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_16_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_16_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_6_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_6_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_8_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_8_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], # enable floating-point tests when lint is fixed # ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]], @@ -280,11 +280,13 @@ if (nightly): for test in derivconfigtests: config = test[0]; tests = test[1]; + if(len(test) >= 3): defines = test[2] + else: defines = "" for t in tests: tc = TestCase( name=t, variant=config, - cmd="vsim > {} -c < {} -c < Date: Fri, 2 Feb 2024 10:45:38 -0600 Subject: [PATCH 5/8] Ugh. This is getting frustrating. Can't seem to get embench to run correctly in new script. --- sim/regression-wally | 94 +++++++++++++++++++++++--------------------- sim/wally-batch.do | 2 +- 2 files changed, 50 insertions(+), 46 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index 7c389be70..f4f23a940 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -220,48 +220,48 @@ if (nightly): ### branch predictor simulation - ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_12_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_12_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_14_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_14_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_16_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_16_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_6_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_6_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_8_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_8_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_12_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_12_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_14_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_14_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_16_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_16_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_6_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_6_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_8_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_2_8_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], # enable floating-point tests when lint is fixed # ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]], @@ -280,13 +280,17 @@ if (nightly): for test in derivconfigtests: config = test[0]; tests = test[1]; - if(len(test) >= 3): defines = test[2] - else: defines = "" + if(len(test) >= 4 and test[2] == "configOptions"): + configOptions = test[3] + cmdPrefix = "vsim > {} -c < {} -c < {} -c < Date: Fri, 2 Feb 2024 15:04:24 -0600 Subject: [PATCH 6/8] Ugh. I can't seem to get questa to set the top level parameters anymore. --- sim/wally-batch.do | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sim/wally-batch.do b/sim/wally-batch.do index 628f361c5..acb40c452 100644 --- a/sim/wally-batch.do +++ b/sim/wally-batch.do @@ -89,11 +89,11 @@ if {$2 eq "buildroot"} { # **** fix this so we can pass any number of +defines. # only allows 3 right now - vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 + vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+PrintHPMCounters=1 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals - vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$4 -o testbenchopt - vsim -lib wkdir/work_${1}_${3}_${4} testbenchopt -fatal 7 -suppress 3829 + vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$3 -o testbenchopt +define+PrintHPMCounters=1 + vsim -lib wkdir/work_${1}_${3}_${4} testbenchopt -fatal 7 -suppress 3829 +define+PrintHPMCounters=1 # Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf #vsim -coverage -lib work_$2 workopt_$2 From cd654d10c14d8b94b999467731e2f147e3da83a5 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sun, 4 Feb 2024 14:13:14 -0600 Subject: [PATCH 7/8] Finally have regression-wally -nightly producing branch predictor results. --- sim/regression-wally | 84 ++++++++++++++++++++++---------------------- sim/wally-batch.do | 6 ++-- 2 files changed, 45 insertions(+), 45 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index f4f23a940..c0e84a8a1 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -220,48 +220,48 @@ if (nightly): ### branch predictor simulation - ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_12_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_12_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_14_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_14_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_16_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_16_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_6_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_6_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_8_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_2_8_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], - ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "configOptions", "+define+PrintHPMCounters=1"], + ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_12_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_12_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_14_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_14_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_16_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_16_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_6_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_6_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_8_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_8_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], # enable floating-point tests when lint is fixed # ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]], diff --git a/sim/wally-batch.do b/sim/wally-batch.do index acb40c452..83a4da90c 100644 --- a/sim/wally-batch.do +++ b/sim/wally-batch.do @@ -89,11 +89,11 @@ if {$2 eq "buildroot"} { # **** fix this so we can pass any number of +defines. # only allows 3 right now - vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+PrintHPMCounters=1 + vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals - vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$3 -o testbenchopt +define+PrintHPMCounters=1 - vsim -lib wkdir/work_${1}_${3}_${4} testbenchopt -fatal 7 -suppress 3829 +define+PrintHPMCounters=1 + vopt wkdir/work_${1}_${3}_${4}.testbench -work wkdir/work_${1}_${3}_${4} -G TEST=$3 ${4} -o testbenchopt + vsim -lib wkdir/work_${1}_${3}_${4} testbenchopt -fatal 7 -suppress 3829 # Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf #vsim -coverage -lib work_$2 workopt_$2 From a2f8d70342e9b8b2fdea88356279fdcf5ef24857 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sun, 4 Feb 2024 16:53:47 -0600 Subject: [PATCH 8/8] Updated branch predictor derivative configs. --- config/derivlist.txt | 27 ++++++++++--------- sim/bp-results/branch-list.txt | 24 ++++++++--------- sim/bp-results/btb-list.txt | 12 ++++----- sim/bp-results/class-list.txt | 12 ++++----- sim/bp-results/ras-list.txt | 10 +++---- sim/regression-wally | 48 ++++++++++++++++++---------------- 6 files changed, 70 insertions(+), 63 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index 558cedbe3..242c803a5 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -285,27 +285,30 @@ RAS_SIZE 32'd4 deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc RAS_SIZE 32'd6 -deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc +deriv bpred_GSHARE_10_10_10_1_rv32gc rv32gc RAS_SIZE 32'd10 deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc RAS_SIZE 32'd16 -deriv bpred_GSHARE_10_2_6_1_rv32gc rv32gc +deriv bpred_GSHARE_10_16_6_1_rv32gc rv32gc BTB_SIZE 32'd6 -deriv bpred_GSHARE_10_2_8_1_rv32gc rv32gc +deriv bpred_GSHARE_10_16_8_1_rv32gc rv32gc BTB_SIZE 32'd8 -deriv bpred_GSHARE_10_2_12_1_rv32gc rv32gc +deriv bpred_GSHARE_10_16_12_1_rv32gc rv32gc BTB_SIZE 32'd12 -deriv bpred_GSHARE_10_2_14_1_rv32gc rv32gc +deriv bpred_GSHARE_10_16_14_1_rv32gc rv32gc BTB_SIZE 32'd14 -deriv bpred_GSHARE_10_2_16_1_rv32gc rv32gc +deriv bpred_GSHARE_10_16_16_1_rv32gc rv32gc BTB_SIZE 32'd16 + + + deriv bpred_GSHARE_6_16_10_0_rv32gc rv32gc bpred_GSHARE_6_16_10_1_rv32gc INSTR_CLASS_PRED 0 @@ -354,25 +357,25 @@ INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_6_10_0_rv32gc rv32gc bpred_GSHARE_10_6_10_1_rv32gc INSTR_CLASS_PRED 0 -deriv bpred_GSHARE_10_2_10_0_rv32gc rv32gc bpred_GSHARE_10_2_10_1_rv32gc +deriv bpred_GSHARE_10_10_10_0_rv32gc rv32gc bpred_GSHARE_10_10_10_1_rv32gc INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_16_10_0_rv32gc rv32gc bpred_GSHARE_10_16_10_1_rv32gc INSTR_CLASS_PRED 0 -deriv bpred_GSHARE_10_2_6_0_rv32gc rv32gc bpred_GSHARE_10_2_6_1_rv32gc +deriv bpred_GSHARE_10_16_6_0_rv32gc rv32gc bpred_GSHARE_10_16_6_1_rv32gc INSTR_CLASS_PRED 0 -deriv bpred_GSHARE_10_2_8_0_rv32gc rv32gc bpred_GSHARE_10_2_8_1_rv32gc +deriv bpred_GSHARE_10_16_8_0_rv32gc rv32gc bpred_GSHARE_10_16_8_1_rv32gc INSTR_CLASS_PRED 0 -deriv bpred_GSHARE_10_2_12_0_rv32gc rv32gc bpred_GSHARE_10_2_12_1_rv32gc +deriv bpred_GSHARE_10_16_12_0_rv32gc rv32gc bpred_GSHARE_10_16_12_1_rv32gc INSTR_CLASS_PRED 0 -deriv bpred_GSHARE_10_2_14_0_rv32gc rv32gc bpred_GSHARE_10_2_14_1_rv32gc +deriv bpred_GSHARE_10_16_14_0_rv32gc rv32gc bpred_GSHARE_10_16_14_1_rv32gc INSTR_CLASS_PRED 0 -deriv bpred_GSHARE_10_2_16_0_rv32gc rv32gc bpred_GSHARE_10_2_16_1_rv32gc +deriv bpred_GSHARE_10_16_16_0_rv32gc rv32gc bpred_GSHARE_10_16_16_1_rv32gc INSTR_CLASS_PRED 0 # Cache configurations diff --git a/sim/bp-results/branch-list.txt b/sim/bp-results/branch-list.txt index 956fc9847..10827b3b9 100644 --- a/sim/bp-results/branch-list.txt +++ b/sim/bp-results/branch-list.txt @@ -1,12 +1,12 @@ -../logs/rv32gc_gshare6.log gshare 6 -../logs/rv32gc_gshare8.log gshare 8 -../logs/rv32gc_gshare10.log gshare 10 -../logs/rv32gc_gshare12.log gshare 12 -../logs/rv32gc_gshare14.log gshare 14 -../logs/rv32gc_gshare16.log gshare 16 -../logs/rv32gc_twobit6.log twobit 6 -../logs/rv32gc_twobit8.log twobit 8 -../logs/rv32gc_twobit10.log twobit 10 -../logs/rv32gc_twobit12.log twobit 12 -../logs/rv32gc_twobit14.log twobit 14 -../logs/rv32gc_twobit16.log twobit 16 +../logs/bpred_GSHARE_6_16_10_0_rv32gc_embench.log gshare 6 +../logs/bpred_GSHARE_8_16_10_0_rv32gc_embench.log gshare 8 +../logs/bpred_GSHARE_10_16_10_0_rv32gc_embench.log gshare 10 +../logs/bpred_GSHARE_12_16_10_0_rv32gc_embench.log gshare 12 +../logs/bpred_GSHARE_14_16_10_0_rv32gc_embench.log gshare 14 +../logs/bpred_GSHARE_16_16_10_0_rv32gc_embench.log gshare 16 +../logs/bpred_TWOBIT_6_16_10_0_rv32gc_embench.log twobit 6 +../logs/bpred_TWOBIT_8_16_10_0_rv32gc_embench.log twobit 8 +../logs/bpred_TWOBIT_10_16_10_0_rv32gc_embench.log twobit 10 +../logs/bpred_TWOBIT_12_16_10_0_rv32gc_embench.log twobit 12 +../logs/bpred_TWOBIT_14_16_10_0_rv32gc_embench.log twobit 14 +../logs/bpred_TWOBIT_16_16_10_0_rv32gc_embench.log twobit 16 diff --git a/sim/bp-results/btb-list.txt b/sim/bp-results/btb-list.txt index 30811459e..a4671ba9f 100644 --- a/sim/bp-results/btb-list.txt +++ b/sim/bp-results/btb-list.txt @@ -1,6 +1,6 @@ -../logs/rv32gc_BTB6.log btb 6 -../logs/rv32gc_BTB8.log btb 8 -../logs/rv32gc_BTB10.log btb 10 -../logs/rv32gc_BTB12.log btb 12 -../logs/rv32gc_BTB14.log btb 14 -../logs/rv32gc_BTB16.log btb 16 +../logs/bpred_GSHARE_16_16_6_0_rv32gc_embench.log btb 6 +../logs/bpred_GSHARE_16_16_8_0_rv32gc_embench.log btb 8 +../logs/bpred_GSHARE_16_16_10_0_rv32gc_embench.log btb 10 +../logs/bpred_GSHARE_16_16_12_0_rv32gc_embench.log btb 12 +../logs/bpred_GSHARE_16_16_14_0_rv32gc_embench.log btb 14 +../logs/bpred_GSHARE_16_16_16_0_rv32gc_embench.log btb 16 diff --git a/sim/bp-results/class-list.txt b/sim/bp-results/class-list.txt index 3926af969..0be63e91a 100644 --- a/sim/bp-results/class-list.txt +++ b/sim/bp-results/class-list.txt @@ -1,6 +1,6 @@ -../logs/rv32gc_class6.log class 6 -../logs/rv32gc_class8.log class 8 -../logs/rv32gc_class10.log class 10 -../logs/rv32gc_class12.log class 12 -../logs/rv32gc_class14.log class 14 -../logs/rv32gc_class16.log class 16 +../logs/bpred_GSHARE_16_16_6_1_rv32gc_embench.log btb 6 +../logs/bpred_GSHARE_16_16_8_1_rv32gc_embench.log btb 8 +../logs/bpred_GSHARE_16_16_10_1_rv32gc_embench.log btb 10 +../logs/bpred_GSHARE_16_16_12_1_rv32gc_embench.log btb 12 +../logs/bpred_GSHARE_16_16_14_1_rv32gc_embench.log btb 14 +../logs/bpred_GSHARE_16_16_16_1_rv32gc_embench.log btb 16 diff --git a/sim/bp-results/ras-list.txt b/sim/bp-results/ras-list.txt index c7628ffaa..c9246b14d 100644 --- a/sim/bp-results/ras-list.txt +++ b/sim/bp-results/ras-list.txt @@ -1,5 +1,5 @@ -../logs/rv32gc_RAS3.log ras 3 -../logs/rv32gc_RAS4.log ras 4 -../logs/rv32gc_RAS6.log ras 6 -../logs/rv32gc_RAS10.log ras 10 -../logs/rv32gc_RAS16.log ras 16 +../logs/bpred_GSHARE_10_3_10_0_rv32gc_embench.log ras 3 +../logs/bpred_GSHARE_10_4_10_0_rv32gc_embench.log ras 4 +../logs/bpred_GSHARE_10_6_10_0_rv32gc_embench.log ras 6 +../logs/bpred_GSHARE_10_10_10_0_rv32gc_embench.log ras 10 +../logs/bpred_GSHARE_10_16_10_0_rv32gc_embench.log ras 16 diff --git a/sim/regression-wally b/sim/regression-wally index c0e84a8a1..4c3b630c4 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -232,36 +232,40 @@ if (nightly): ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + + ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_2_12_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_2_12_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_2_14_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_2_14_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_2_16_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_2_16_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_2_6_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_2_6_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_2_8_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_2_8_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + + # btb + ["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + + # ras + ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + ["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], + # enable floating-point tests when lint is fixed # ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],