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partial dcache reorg.

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This commit is contained in:
Ross Thompson 2021-08-25 12:42:05 -05:00
parent 699053bab0
commit a99b5f648b
3 changed files with 28 additions and 20 deletions
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38
wally-pipelined/src/cache/DCacheMem.sv vendored
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@ -25,25 +25,28 @@
`include "wally-config.vh" `include "wally-config.vh"
module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26) module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
parameter OFFSETLEN, parameter INDEXLEN)
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic [$clog2(NUMLINES)-1:0] Adr, input logic [$clog2(NUMLINES)-1:0] Adr,
input logic WriteEnable, input logic [`PA_BITS-1:OFFSETLEN+INDEXLEN] MemPAdrM,
input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable, input logic WriteEnable,
input logic TagWriteEnable, input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable,
input logic [BLOCKLEN-1:0] WriteData, input logic TagWriteEnable,
input logic [TAGLEN-1:0] WriteTag, input logic [BLOCKLEN-1:0] WriteData,
input logic SetValid, input logic [TAGLEN-1:0] WriteTag,
input logic ClearValid, input logic SetValid,
input logic SetDirty, input logic ClearValid,
input logic ClearDirty, input logic SetDirty,
input logic ClearDirty,
output logic [BLOCKLEN-1:0] ReadData, output logic [BLOCKLEN-1:0] ReadData,
output logic [TAGLEN-1:0] ReadTag, output logic [TAGLEN-1:0] ReadTag,
output logic Valid, output logic Valid,
output logic Dirty output logic Dirty,
output logic WayHit
); );
logic [NUMLINES-1:0] ValidBits, DirtyBits; logic [NUMLINES-1:0] ValidBits, DirtyBits;
@ -71,6 +74,9 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26
.WriteData(WriteTag), .WriteData(WriteTag),
.WriteEnable(TagWriteEnable)); .WriteEnable(TagWriteEnable));
assign WayHit = Valid & (ReadTag == MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
always_ff @(posedge clk, posedge reset) begin always_ff @(posedge clk, posedge reset) begin
if (reset) if (reset)

8
wally-pipelined/src/cache/dcache.sv vendored
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@ -208,10 +208,12 @@ module dcache
genvar way; genvar way;
generate generate
for(way = 0; way < NUMWAYS; way = way + 1) begin :CacheWays for(way = 0; way < NUMWAYS; way = way + 1) begin :CacheWays
DCacheMem #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN)) DCacheMem #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN),
.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
MemWay(.clk(clk), MemWay(.clk(clk),
.reset(reset), .reset(reset),
.Adr(SRAMAdr), .Adr(SRAMAdr),
.MemPAdrM(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
.WriteEnable(SRAMWayWriteEnable[way]), .WriteEnable(SRAMWayWriteEnable[way]),
.WriteWordEnable(SRAMWordEnable), .WriteWordEnable(SRAMWordEnable),
.TagWriteEnable(SRAMBlockWayWriteEnableM[way]), .TagWriteEnable(SRAMBlockWayWriteEnableM[way]),
@ -224,8 +226,8 @@ module dcache
.ReadData(ReadDataBlockWayM[way]), .ReadData(ReadDataBlockWayM[way]),
.ReadTag(ReadTag[way]), .ReadTag(ReadTag[way]),
.Valid(Valid[way]), .Valid(Valid[way]),
.Dirty(Dirty[way])); .Dirty(Dirty[way]),
assign WayHit[way] = Valid[way] & (ReadTag[way] == MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]); .WayHit(WayHit[way]));
assign SelectedWay[way] = SelEvict ? VictimWay[way] : WayHit[way]; assign SelectedWay[way] = SelEvict ? VictimWay[way] : WayHit[way];
assign ReadDataBlockWayMaskedM[way] = SelectedWay[way] ? ReadDataBlockWayM[way] : '0; // first part of AO mux. assign ReadDataBlockWayMaskedM[way] = SelectedWay[way] ? ReadDataBlockWayM[way] : '0; // first part of AO mux.

2
wally-pipelined/src/mmu/mmu.sv
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@ -26,7 +26,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
parameter IMMU = 0) ( parameter IMMU = 0) (
input logic clk, reset, input logic clk, reset,