From a99b5f648b785251f3106bc0767c79977ead339e Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Wed, 25 Aug 2021 12:42:05 -0500
Subject: [PATCH] partial dcache reorg.

---
 wally-pipelined/src/cache/DCacheMem.sv | 38 +++++++++++++++-----------
 wally-pipelined/src/cache/dcache.sv    |  8 ++++--
 wally-pipelined/src/mmu/mmu.sv         |  2 +-
 3 files changed, 28 insertions(+), 20 deletions(-)

diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/DCacheMem.sv
index 18752ed6c..2e99917b2 100644
--- a/wally-pipelined/src/cache/DCacheMem.sv
+++ b/wally-pipelined/src/cache/DCacheMem.sv
@@ -25,25 +25,28 @@
 
 `include "wally-config.vh"
 
-module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26) 
+module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
+		   parameter OFFSETLEN, parameter INDEXLEN) 
   (input logic 		       clk,
-   input logic 			      reset,
+   input logic 				       reset,
 
-   input logic [$clog2(NUMLINES)-1:0] Adr,
-   input logic 			      WriteEnable,
-   input logic [BLOCKLEN/`XLEN-1:0]   WriteWordEnable,
-   input logic TagWriteEnable,
-   input logic [BLOCKLEN-1:0] 	      WriteData,
-   input logic [TAGLEN-1:0] 	      WriteTag,
-   input logic 			      SetValid,
-   input logic 			      ClearValid,
-   input logic 			      SetDirty,
-   input logic 			      ClearDirty,
+   input logic [$clog2(NUMLINES)-1:0] 	       Adr,
+   input logic [`PA_BITS-1:OFFSETLEN+INDEXLEN] MemPAdrM,
+   input logic 				       WriteEnable,
+   input logic [BLOCKLEN/`XLEN-1:0] 	       WriteWordEnable,
+   input logic 				       TagWriteEnable,
+   input logic [BLOCKLEN-1:0] 		       WriteData,
+   input logic [TAGLEN-1:0] 		       WriteTag,
+   input logic 				       SetValid,
+   input logic 				       ClearValid,
+   input logic 				       SetDirty,
+   input logic 				       ClearDirty,
 
-   output logic [BLOCKLEN-1:0] 	      ReadData,
-   output logic [TAGLEN-1:0] 	      ReadTag,
-   output logic 		      Valid,
-   output logic 		      Dirty
+   output logic [BLOCKLEN-1:0] 		       ReadData,
+   output logic [TAGLEN-1:0] 		       ReadTag,
+   output logic 			       Valid,
+   output logic 			       Dirty,
+   output logic 			       WayHit
    );
 
   logic [NUMLINES-1:0] 		      ValidBits, DirtyBits;
@@ -71,6 +74,9 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26
 	      .WriteData(WriteTag),
 	      .WriteEnable(TagWriteEnable));
 
+  assign WayHit = Valid & (ReadTag == MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
+  
+
   
   always_ff @(posedge clk, posedge reset) begin
     if (reset) 
diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index 682a8be77..ede050e1a 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -208,10 +208,12 @@ module dcache
   genvar		       way;
   generate
     for(way = 0; way < NUMWAYS; way = way + 1) begin :CacheWays
-      DCacheMem #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN))
+      DCacheMem #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), 
+		  .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
       MemWay(.clk(clk),
 	     .reset(reset),
 	     .Adr(SRAMAdr),
+	     .MemPAdrM(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
 	     .WriteEnable(SRAMWayWriteEnable[way]),
 	     .WriteWordEnable(SRAMWordEnable),
 	     .TagWriteEnable(SRAMBlockWayWriteEnableM[way]), 
@@ -224,8 +226,8 @@ module dcache
 	     .ReadData(ReadDataBlockWayM[way]),
 	     .ReadTag(ReadTag[way]),
 	     .Valid(Valid[way]),
-	     .Dirty(Dirty[way]));
-      assign WayHit[way] = Valid[way] & (ReadTag[way] == MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
+	     .Dirty(Dirty[way]),
+	     .WayHit(WayHit[way]));
       assign SelectedWay[way] = SelEvict ? VictimWay[way] : WayHit[way];
       assign ReadDataBlockWayMaskedM[way] = SelectedWay[way] ? ReadDataBlockWayM[way] : '0;  // first part of AO mux.
 
diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv
index cea862f1b..1995f09a0 100644
--- a/wally-pipelined/src/mmu/mmu.sv
+++ b/wally-pipelined/src/mmu/mmu.sv
@@ -26,7 +26,7 @@
 
 `include "wally-config.vh"
 
-module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
+module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
              parameter IMMU = 0) (
 
   input logic              clk, reset,