Update plic_apb.sv

Program clean up
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Harshini Srinath 2023-06-15 10:08:16 -07:00 committed by GitHub
parent afa0bcdd16
commit a9495e8595
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@ -97,6 +97,7 @@ module plic_apb import cvw::*; #(parameter cvw_t P) (
// ==================
// Register Interface
// ==================
always @(posedge PCLK) begin
// resetting
if (~PRESETn) begin
@ -245,4 +246,3 @@ module plic_apb import cvw::*; #(parameter cvw_t P) (
assign MExtInt = |(threshMask[0] & priorities_with_irqs[0]);
assign SExtInt = |(threshMask[1] & priorities_with_irqs[1]);
endmodule