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Started pagetablewalker cleanup: combined state flops shared for both RV versions

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This commit is contained in:
David Harris 2021-07-17 02:53:52 -04:00
parent b65788d165
commit a8a5fa4b3c
1 changed files with 2 additions and 16 deletions
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18
wally-pipelined/src/mmu/pagetablewalker.sv
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@ -151,6 +151,8 @@ module pagetablewalker
.d(ITLBMissF), .d(ITLBMissF),
.q(ITLBMissFQ)); .q(ITLBMissFQ));
flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
assign AnyTLBMissM = DTLBMissM | ITLBMissF; assign AnyTLBMissM = DTLBMissM | ITLBMissF;
@ -174,9 +176,6 @@ module pagetablewalker
if (`XLEN == 32) begin if (`XLEN == 32) begin
logic [9:0] VPN1, VPN0; logic [9:0] VPN1, VPN0;
flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
// State transition logic // State transition logic
always_comb begin always_comb begin
@ -318,19 +317,6 @@ module pagetablewalker
logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage;
flopenl #(.TYPE(statetype)) WalkerStageReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState);
/* -----\/----- EXCLUDED -----\/-----
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV ||
WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall;
-----/\----- EXCLUDED -----/\----- */
//assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 ||
// WalkerState == LEVEL2 || WalkerState == LEVEL1;
always_comb begin always_comb begin
PRegEn = 1'b0; PRegEn = 1'b0;
TranslationPAdr = '0; TranslationPAdr = '0;