From a8a5fa4b3c0b2fc098ab083f54667f18c9cf9631 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jul 2021 02:53:52 -0400 Subject: [PATCH] Started pagetablewalker cleanup: combined state flops shared for both RV versions --- wally-pipelined/src/mmu/pagetablewalker.sv | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index ea4c4de3f..528b72920 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -151,6 +151,8 @@ module pagetablewalker .d(ITLBMissF), .q(ITLBMissFQ)); + flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); assign AnyTLBMissM = DTLBMissM | ITLBMissF; @@ -174,9 +176,6 @@ module pagetablewalker if (`XLEN == 32) begin logic [9:0] VPN1, VPN0; - flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); - - flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); // State transition logic always_comb begin @@ -318,19 +317,6 @@ module pagetablewalker logic TerapageMisaligned, GigapageMisaligned, BadTerapage, BadGigapage; - flopenl #(.TYPE(statetype)) WalkerStageReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); - - flopenl #(.TYPE(statetype)) PreviousWalkerStateReg(clk, reset, 1'b1, WalkerState, IDLE, PreviousWalkerState); - - /* -----\/----- EXCLUDED -----\/----- - assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV || - WalkerState == LEVEL2_WDV || WalkerState == LEVEL3_WDV) && ~HPTWStall; - -----/\----- EXCLUDED -----/\----- */ - - //assign HPTWRead = (WalkerState == IDLE && HPTWTranslate) || WalkerState == LEVEL3 || - // WalkerState == LEVEL2 || WalkerState == LEVEL1; - - always_comb begin PRegEn = 1'b0; TranslationPAdr = '0;