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Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.

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This commit is contained in:
Ross Thompson 2022-07-17 21:05:31 -05:00
parent 3670c47141
commit a88543275f
2 changed files with 47 additions and 27 deletions
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15
pipelined/src/cache/cacheway.sv vendored
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@ -115,12 +115,27 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
assign WordByteEnabled[BYTESPERWORD*(words+1)-1:BYTESPERWORD*(words)] = {{BYTESPERWORD}{SelectedWriteWordEn[words]}};
assign SRAMLineByteMask = ReplicatedByteMask & WordByteEnabled;
localparam integer SRAMLEN = 256;
localparam integer NUMSRAM = LINELEN/SRAMLEN;
localparam integer SRAMLENINBYTES = SRAMLEN/8;
localparam integer LOGNUMSRAM = $clog2(NUMSRAM);
for(words = 0; words < NUMSRAM; words++) begin: word
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .Adr(RAdr),
.ReadData(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
.CacheWriteData(CacheWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
.WriteEnable(1'b1), .ByteMask(SRAMLineByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
end
/* -----\/----- EXCLUDED -----\/-----
for(words = 0; words < 1; words++) begin: word
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(LINELEN)) CacheDataMem(.clk, .Adr(RAdr),
.ReadData(ReadDataLine),
.CacheWriteData(CacheWriteData),
.WriteEnable(1'b1), .ByteMask(SRAMLineByteMask));
end
-----/\----- EXCLUDED -----/\----- */
/* -----\/----- EXCLUDED -----\/-----

39
pipelined/testbench/testbench.sv
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@ -430,8 +430,11 @@ module DCacheFlushFSM
localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
localparam integer cachenumwords = 1; //testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN;
localparam integer numwords = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN;
localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM;
localparam integer numwords = sramlen/`XLEN;
localparam integer lognumlines = $clog2(numlines);
localparam integer loglinebytelen = $clog2(linebytelen);
localparam integer lognumways = $clog2(numways);
@ -440,17 +443,17 @@ module DCacheFlushFSM
genvar index, way, cacheWord;
logic [linelen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachenumwords-1:0];
logic [linelen-1:0] cacheline;
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachenumwords-1:0];
logic CacheValid [numways-1:0] [numlines-1:0] [cachenumwords-1:0];
logic CacheDirty [numways-1:0] [numlines-1:0] [cachenumwords-1:0];
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachenumwords-1:0];
logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic [sramlen-1:0] cacheline;
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
for(index = 0; index < numlines; index++) begin
for(way = 0; way < numways; way++) begin
for(cacheWord = 0; cacheWord < cachenumwords; cacheWord++) begin
for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
copyShadow #(.tagstart(tagstart),
.loglinebytelen(loglinebytelen), .linelen(linelen))
.loglinebytelen(loglinebytelen), .sramlen(sramlen))
copyShadow(.clk,
.start,
.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]),
@ -468,21 +471,23 @@ module DCacheFlushFSM
end
end
integer i, j, k;
integer i, j, k, l;
always @(posedge clk) begin
if (start) begin #1
#1
for(i = 0; i < numlines; i++) begin
for(j = 0; j < numways; j++) begin
if (CacheValid[j][i][0] & CacheDirty[j][i][0]) begin
for(l = 0; l < cachesramwords; l++) begin
if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
for(k = 0; k < numwords; k++) begin
//cacheline = CacheData[j][i][0];
// does not work with modelsim
// # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
// see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
//ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k];
ShadowRAM[(CacheAdr[j][i][0] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][0][`XLEN*k +: `XLEN];
ShadowRAM[(CacheAdr[j][i][l] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][l][`XLEN*k +: `XLEN];
end
end
end
end
@ -494,15 +499,15 @@ module DCacheFlushFSM
endmodule
module copyShadow
#(parameter tagstart, loglinebytelen, linelen)
#(parameter tagstart, loglinebytelen, sramlen)
(input logic clk,
input logic start,
input logic [`PA_BITS-1:tagstart] tag,
input logic valid, dirty,
input logic [linelen-1:0] data,
input logic [sramlen-1:0] data,
input logic [32-1:0] index,
input logic [32-1:0] cacheWord,
output logic [linelen-1:0] CacheData,
output logic [sramlen-1:0] CacheData,
output logic [`PA_BITS-1:0] CacheAdr,
output logic [`XLEN-1:0] CacheTag,
output logic CacheValid,
@ -515,7 +520,7 @@ module copyShadow
CacheValid = valid;
CacheDirty = dirty;
CacheData = data;
CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8));
CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8));
end
end