From a88543275fee66d801ad503abeb53d0469123c3e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 17 Jul 2022 21:05:31 -0500 Subject: [PATCH] Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN. --- pipelined/src/cache/cacheway.sv | 17 +++++++++- pipelined/testbench/testbench.sv | 57 +++++++++++++++++--------------- 2 files changed, 47 insertions(+), 27 deletions(-) diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 6aedff816..5397375a0 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -115,13 +115,28 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, assign WordByteEnabled[BYTESPERWORD*(words+1)-1:BYTESPERWORD*(words)] = {{BYTESPERWORD}{SelectedWriteWordEn[words]}}; assign SRAMLineByteMask = ReplicatedByteMask & WordByteEnabled; + localparam integer SRAMLEN = 256; + localparam integer NUMSRAM = LINELEN/SRAMLEN; + localparam integer SRAMLENINBYTES = SRAMLEN/8; + localparam integer LOGNUMSRAM = $clog2(NUMSRAM); + + for(words = 0; words < NUMSRAM; words++) begin: word + sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .Adr(RAdr), + .ReadData(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), + .CacheWriteData(CacheWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), + .WriteEnable(1'b1), .ByteMask(SRAMLineByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); + end + + +/* -----\/----- EXCLUDED -----\/----- for(words = 0; words < 1; words++) begin: word sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(LINELEN)) CacheDataMem(.clk, .Adr(RAdr), .ReadData(ReadDataLine), .CacheWriteData(CacheWriteData), .WriteEnable(1'b1), .ByteMask(SRAMLineByteMask)); end - + -----/\----- EXCLUDED -----/\----- */ + /* -----\/----- EXCLUDED -----\/----- for(words = 0; words < WORDSPERLINE; words++) begin: word diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 5d74ed9ee..0179d1d14 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -429,10 +429,13 @@ module DCacheFlushFSM localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; - localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; - localparam integer cachenumwords = 1; //testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN; - localparam integer numwords = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN; - localparam integer lognumlines = $clog2(numlines); + localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; + localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; + localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; + +//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM; + localparam integer numwords = sramlen/`XLEN; + localparam integer lognumlines = $clog2(numlines); localparam integer loglinebytelen = $clog2(linebytelen); localparam integer lognumways = $clog2(numways); localparam integer tagstart = lognumlines + loglinebytelen; @@ -440,17 +443,17 @@ module DCacheFlushFSM genvar index, way, cacheWord; - logic [linelen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachenumwords-1:0]; - logic [linelen-1:0] cacheline; - logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachenumwords-1:0]; - logic CacheValid [numways-1:0] [numlines-1:0] [cachenumwords-1:0]; - logic CacheDirty [numways-1:0] [numlines-1:0] [cachenumwords-1:0]; - logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachenumwords-1:0]; + logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic [sramlen-1:0] cacheline; + logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; for(index = 0; index < numlines; index++) begin for(way = 0; way < numways; way++) begin - for(cacheWord = 0; cacheWord < cachenumwords; cacheWord++) begin + for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin copyShadow #(.tagstart(tagstart), - .loglinebytelen(loglinebytelen), .linelen(linelen)) + .loglinebytelen(loglinebytelen), .sramlen(sramlen)) copyShadow(.clk, .start, .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]), @@ -468,23 +471,25 @@ module DCacheFlushFSM end end - integer i, j, k; + integer i, j, k, l; always @(posedge clk) begin if (start) begin #1 #1 for(i = 0; i < numlines; i++) begin for(j = 0; j < numways; j++) begin - if (CacheValid[j][i][0] & CacheDirty[j][i][0]) begin - for(k = 0; k < numwords; k++) begin - //cacheline = CacheData[j][i][0]; - // does not work with modelsim - // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions. - // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions - //ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k]; - ShadowRAM[(CacheAdr[j][i][0] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][0][`XLEN*k +: `XLEN]; + for(l = 0; l < cachesramwords; l++) begin + if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin + for(k = 0; k < numwords; k++) begin + //cacheline = CacheData[j][i][0]; + // does not work with modelsim + // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions. + // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions + //ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k]; + ShadowRAM[(CacheAdr[j][i][l] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][l][`XLEN*k +: `XLEN]; + end + end end - end end end end @@ -494,15 +499,15 @@ module DCacheFlushFSM endmodule module copyShadow - #(parameter tagstart, loglinebytelen, linelen) + #(parameter tagstart, loglinebytelen, sramlen) (input logic clk, input logic start, input logic [`PA_BITS-1:tagstart] tag, input logic valid, dirty, - input logic [linelen-1:0] data, + input logic [sramlen-1:0] data, input logic [32-1:0] index, input logic [32-1:0] cacheWord, - output logic [linelen-1:0] CacheData, + output logic [sramlen-1:0] CacheData, output logic [`PA_BITS-1:0] CacheAdr, output logic [`XLEN-1:0] CacheTag, output logic CacheValid, @@ -515,7 +520,7 @@ module copyShadow CacheValid = valid; CacheDirty = dirty; CacheData = data; - CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8)); + CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8)); end end