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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Renamed signals to be consistent with textbook.
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@ -101,7 +101,7 @@ module ifu (
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logic [`XLEN-1:0] PCNextF; // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
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logic [`XLEN-1:0] PCNextF; // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
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logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
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logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
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logic [`XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
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logic [`XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
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logic [`XLEN-1:0] PCNextFSpill; // Next PCF after possible + 2 to handle spill
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logic [`XLEN-1:0] PCSpillNextF; // Next PCF after possible + 2 to handle spill
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logic [`XLEN-1:0] PCLinkD; // PCF2or4F delayed 1 cycle. This is next PC after a control flow instruction (br or j)
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logic [`XLEN-1:0] PCLinkD; // PCF2or4F delayed 1 cycle. This is next PC after a control flow instruction (br or j)
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logic [`XLEN-1:2] PCPlus4F; // PCPlus4F is always PCF + 4. Fancy way to compute PCPlus2or4F
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logic [`XLEN-1:2] PCPlus4F; // PCPlus4F is always PCF + 4. Fancy way to compute PCPlus2or4F
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logic [`XLEN-1:0] PCD; // Decode stage instruction address
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logic [`XLEN-1:0] PCD; // Decode stage instruction address
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@ -126,7 +126,7 @@ module ifu (
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logic CacheableF; // PMA indicates instruction address is cacheable
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logic CacheableF; // PMA indicates instruction address is cacheable
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logic SelNextSpillF; // In a spill, stall pipeline and gate local stallF
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logic SelSpillNextF; // In a spill, stall pipeline and gate local stallF
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logic BusStall; // Bus interface busy with multicycle operation
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logic BusStall; // Bus interface busy with multicycle operation
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logic IFUCacheBusStallD; // EIther I$ or bus busy with multicycle operation
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logic IFUCacheBusStallD; // EIther I$ or bus busy with multicycle operation
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logic GatedStallD; // StallD gated by selected next spill
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logic GatedStallD; // StallD gated by selected next spill
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@ -144,12 +144,12 @@ module ifu (
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if(`C_SUPPORTED) begin : Spill
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if(`C_SUPPORTED) begin : Spill
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spill #(`ICACHE_SUPPORTED) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
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spill #(`ICACHE_SUPPORTED) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
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.InstrUpdateDAF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCSpillF, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
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.InstrUpdateDAF, .IFUCacheBusStallD, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
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end else begin : NoSpill
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end else begin : NoSpill
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assign PCNextFSpill = PCNextF;
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assign PCSpillNextF = PCNextF;
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assign PCSpillF = PCF;
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assign PCSpillF = PCF;
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assign PostSpillInstrRawF = InstrRawF;
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assign PostSpillInstrRawF = InstrRawF;
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assign {SelNextSpillF, CompressedF} = 0;
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assign {SelSpillNextF, CompressedF} = 0;
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end
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end
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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@ -213,7 +213,7 @@ module ifu (
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logic IROMce;
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logic IROMce;
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assign IROMce = ~GatedStallD | reset;
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assign IROMce = ~GatedStallD | reset;
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assign IFURWF = 2'b10;
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assign IFURWF = 2'b10;
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irom irom(.clk, .ce(IROMce), .Adr(PCNextFSpill[`XLEN-1:0]), .IROMInstrF);
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irom irom(.clk, .ce(IROMce), .Adr(PCSpillNextF[`XLEN-1:0]), .IROMInstrF);
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end else begin
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end else begin
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assign IFURWF = 2'b10;
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assign IFURWF = 2'b10;
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end
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end
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@ -245,7 +245,7 @@ module ifu (
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.CacheWriteData('0),
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.CacheWriteData('0),
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.CacheRW(CacheRWF),
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.CacheRW(CacheRWF),
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.CacheAtomic('0), .FlushCache('0),
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.CacheAtomic('0), .FlushCache('0),
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.NextAdr(PCNextFSpill[11:0]),
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.NextAdr(PCSpillNextF[11:0]),
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.PAdr(PCPF),
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.PAdr(PCPF),
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.CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));
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.CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));
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ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW)
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ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW)
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@ -286,8 +286,8 @@ module ifu (
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end
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end
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assign IFUCacheBusStallD = ICacheStallF | BusStall;
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assign IFUCacheBusStallD = ICacheStallF | BusStall;
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assign IFUStallF = IFUCacheBusStallD | SelNextSpillF;
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assign IFUStallF = IFUCacheBusStallD | SelSpillNextF;
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assign GatedStallD = StallD & ~SelNextSpillF;
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assign GatedStallD = StallD & ~SelSpillNextF;
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flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
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flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
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@ -43,9 +43,9 @@ module spill #(
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input logic IFUCacheBusStallD, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
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input logic IFUCacheBusStallD, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
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input logic ITLBMissF, // ITLB miss, ignore memory request
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input logic ITLBMissF, // ITLB miss, ignore memory request
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input logic InstrUpdateDAF, // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active)
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input logic InstrUpdateDAF, // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active)
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output logic [`XLEN-1:0] PCNextFSpill, // The next PCF for one of the two memory addresses of the spill
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output logic [`XLEN-1:0] PCSpillNextF, // The next PCF for one of the two memory addresses of the spill
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output logic [`XLEN-1:0] PCSpillF, // PCF for one of the two memory addresses of the spill
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output logic [`XLEN-1:0] PCSpillF, // PCF for one of the two memory addresses of the spill
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output logic SelNextSpillF, // During the transition between the two spill operations, the IFU should stall the pipeline
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output logic SelSpillNextF, // During the transition between the two spill operations, the IFU should stall the pipeline
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output logic [31:0] PostSpillInstrRawF,// The final 32 bit instruction after merging the two spilled fetches into 1 instruction
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output logic [31:0] PostSpillInstrRawF,// The final 32 bit instruction after merging the two spilled fetches into 1 instruction
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output logic CompressedF); // The fetched instruction is compressed
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output logic CompressedF); // The fetched instruction is compressed
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@ -67,7 +67,7 @@ module spill #(
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// compute PCF+2 from the raw PC+4
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// compute PCF+2 from the raw PC+4
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mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlus4F, 2'b00}), .s(PCF[1]), .y(PCPlus2F));
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mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlus4F, 2'b00}), .s(PCF[1]), .y(PCPlus2F));
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// select between PCNextF and PCF+2
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// select between PCNextF and PCF+2
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mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~FlushD), .y(PCNextFSpill));
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mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelSpillNextF & ~FlushD), .y(PCSpillNextF));
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// select between PCF and PCF+2
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// select between PCF and PCF+2
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mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCSpillF));
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mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCSpillF));
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@ -94,7 +94,7 @@ module spill #(
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end
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end
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assign SelSpillF = (CurrState == STATE_SPILL);
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assign SelSpillF = (CurrState == STATE_SPILL);
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assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) | (CurrState == STATE_SPILL & IFUCacheBusStallD);
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assign SelSpillNextF = (CurrState == STATE_READY & TakeSpillF) | (CurrState == STATE_SPILL & IFUCacheBusStallD);
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assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF & ~FlushD;
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assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF & ~FlushD;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////////
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