diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index fa3eab16f..41b0de00e 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -101,7 +101,7 @@ module ifu (
   logic [`XLEN-1:0]            PCNextF;    // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
   logic                        BranchMisalignedFaultE;                // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
   logic [`XLEN-1:0] 		   PCPlus2or4F;                           // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
-  logic [`XLEN-1:0]			   PCNextFSpill;                          // Next PCF after possible + 2 to handle spill
+  logic [`XLEN-1:0]			   PCSpillNextF;                          // Next PCF after possible + 2 to handle spill
   logic [`XLEN-1:0]            PCLinkD;                               // PCF2or4F delayed 1 cycle.  This is next PC after a control flow instruction (br or j)
   logic [`XLEN-1:2]            PCPlus4F;                              // PCPlus4F is always PCF + 4.  Fancy way to compute PCPlus2or4F
   logic [`XLEN-1:0]            PCD;                                   // Decode stage instruction address
@@ -126,7 +126,7 @@ module ifu (
 
 
   logic 					   CacheableF;                            // PMA indicates instruction address is cacheable
-  logic 					   SelNextSpillF;                         // In a spill, stall pipeline and gate local stallF
+  logic 					   SelSpillNextF;                         // In a spill, stall pipeline and gate local stallF
   logic 					   BusStall;                              // Bus interface busy with multicycle operation
   logic 					   IFUCacheBusStallD;                     // EIther I$ or bus busy with multicycle operation
   logic 					   GatedStallD;                           // StallD gated by selected next spill
@@ -144,12 +144,12 @@ module ifu (
 
   if(`C_SUPPORTED) begin : Spill
     spill #(`ICACHE_SUPPORTED) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
-      .InstrUpdateDAF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCSpillF, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
+      .InstrUpdateDAF, .IFUCacheBusStallD, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
   end else begin : NoSpill
-    assign PCNextFSpill = PCNextF;
+    assign PCSpillNextF = PCNextF;
     assign PCSpillF = PCF;
     assign PostSpillInstrRawF = InstrRawF;
-    assign {SelNextSpillF, CompressedF} = 0;
+    assign {SelSpillNextF, CompressedF} = 0;
   end
 
   ////////////////////////////////////////////////////////////////////////////////////////////////
@@ -213,7 +213,7 @@ module ifu (
 	logic IROMce;
 	assign IROMce = ~GatedStallD | reset;
     assign IFURWF = 2'b10;
-    irom irom(.clk, .ce(IROMce), .Adr(PCNextFSpill[`XLEN-1:0]), .IROMInstrF);
+    irom irom(.clk, .ce(IROMce), .Adr(PCSpillNextF[`XLEN-1:0]), .IROMInstrF);
   end else begin
     assign IFURWF = 2'b10;
   end
@@ -245,7 +245,7 @@ module ifu (
              .CacheWriteData('0),
              .CacheRW(CacheRWF), 
              .CacheAtomic('0), .FlushCache('0),
-             .NextAdr(PCNextFSpill[11:0]),
+             .NextAdr(PCSpillNextF[11:0]),
              .PAdr(PCPF),
              .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));
       ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW) 
@@ -286,8 +286,8 @@ module ifu (
   end
   
   assign IFUCacheBusStallD = ICacheStallF | BusStall;
-  assign IFUStallF = IFUCacheBusStallD | SelNextSpillF;
-  assign GatedStallD = StallD & ~SelNextSpillF;
+  assign IFUStallF = IFUCacheBusStallD | SelSpillNextF;
+  assign GatedStallD = StallD & ~SelSpillNextF;
   
   flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
 
diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv
index d4e85faf0..73f302ca9 100644
--- a/src/ifu/spill.sv
+++ b/src/ifu/spill.sv
@@ -43,9 +43,9 @@ module spill #(
   input logic 			   IFUCacheBusStallD, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
   input logic 			   ITLBMissF,         // ITLB miss, ignore memory request
   input logic 			   InstrUpdateDAF, // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active)
-  output logic [`XLEN-1:0] PCNextFSpill,      // The next PCF for one of the two memory addresses of the spill
+  output logic [`XLEN-1:0] PCSpillNextF,      // The next PCF for one of the two memory addresses of the spill
   output logic [`XLEN-1:0] PCSpillF,          // PCF for one of the two memory addresses of the spill
-  output logic 			   SelNextSpillF,     // During the transition between the two spill operations, the IFU should stall the pipeline
+  output logic 			   SelSpillNextF,     // During the transition between the two spill operations, the IFU should stall the pipeline
   output logic [31:0] 	   PostSpillInstrRawF,// The final 32 bit instruction after merging the two spilled fetches into 1 instruction
   output logic 			   CompressedF);      // The fetched instruction is compressed
 
@@ -57,7 +57,7 @@ module spill #(
   logic                TakeSpillF;
   logic                SpillF;
   logic                SelSpillF;
-  logic 			         SpillSaveF;
+  logic 			   SpillSaveF;
   logic [15:0]         InstrFirstHalfF;
 
   ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -67,7 +67,7 @@ module spill #(
   // compute PCF+2 from the raw PC+4
   mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlus4F, 2'b00}), .s(PCF[1]), .y(PCPlus2F));
   // select between PCNextF and PCF+2
-  mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~FlushD), .y(PCNextFSpill));
+  mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelSpillNextF & ~FlushD), .y(PCSpillNextF));
   // select between PCF and PCF+2
   mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCSpillF));
 
@@ -94,7 +94,7 @@ module spill #(
   end
 
   assign SelSpillF = (CurrState == STATE_SPILL);
-  assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) | (CurrState == STATE_SPILL & IFUCacheBusStallD);
+  assign SelSpillNextF = (CurrState == STATE_READY & TakeSpillF) | (CurrState == STATE_SPILL & IFUCacheBusStallD);
   assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF & ~FlushD;
 
   ////////////////////////////////////////////////////////////////////////////////////////////////////