Fixed first problem with the rv64i IROM.

This commit is contained in:
Ross Thompson 2022-10-11 11:35:40 -05:00
parent 403daecc8e
commit a5c15fd801

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@ -42,6 +42,11 @@ module irom(
rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataFull));
if (`XLEN == 32) assign ReadData = ReadDataFull;
else assign ReadData = Adr[OFFSET] ? ReadDataFull[63:32] : ReadDataFull[31:0];
// have to delay Ardr[OFFSET-1] by 1 cycle
else begin
logic AdrD;
flopen #(1) AdrReg(clk, ce, Adr[OFFSET-1], AdrD);
assign ReadData = AdrD ? ReadDataFull[63:32] : ReadDataFull[31:0];
end
endmodule