diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv
index 981eadb08..af262ba8b 100644
--- a/pipelined/src/ifu/irom.sv
+++ b/pipelined/src/ifu/irom.sv
@@ -42,6 +42,11 @@ module irom(
 
   rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataFull));
   if (`XLEN == 32) assign ReadData = ReadDataFull;
-  else             assign ReadData = Adr[OFFSET] ? ReadDataFull[63:32] : ReadDataFull[31:0];
+  // have to delay Ardr[OFFSET-1] by 1 cycle
+  else             begin
+    logic AdrD;
+    flopen #(1) AdrReg(clk, ce, Adr[OFFSET-1], AdrD);
+    assign ReadData = AdrD ? ReadDataFull[63:32] : ReadDataFull[31:0];
+  end
 endmodule