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added one bit muxes for data critical synths

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Madeleine Masser-Frye 2022-06-09 00:06:12 +00:00
parent fbd384680e
commit a54837b102
1 changed files with 24 additions and 0 deletions
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pipelined/src/ppa/ppa.sv
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@ -525,6 +525,30 @@ module ppa_decoder #(parameter WIDTH = 8) (
end end
endmodule endmodule
module ppa_mux2_1 #(parameter WIDTH = 1) (
input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule
module ppa_mux4_1 #(parameter WIDTH = 1) (
input logic [WIDTH-1:0] d0, d1, d2, d3,
input logic [1:0] s,
output logic [WIDTH-1:0] y);
assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
endmodule
module ppa_mux8_1 #(parameter WIDTH = 1) (
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
input logic [2:0] s,
output logic [WIDTH-1:0] y);
assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
endmodule
module ppa_mux2_8 #(parameter WIDTH = 8) ( module ppa_mux2_8 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, input logic [WIDTH-1:0] d0, d1,
input logic s, input logic s,