From a54837b10267130ca55c6ae2d3568618c533cc87 Mon Sep 17 00:00:00 2001
From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com>
Date: Thu, 9 Jun 2022 00:06:12 +0000
Subject: [PATCH] added one bit muxes for data critical synths

---
 pipelined/src/ppa/ppa.sv | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv
index b5df310d2..31aa13523 100644
--- a/pipelined/src/ppa/ppa.sv
+++ b/pipelined/src/ppa/ppa.sv
@@ -525,6 +525,30 @@ module ppa_decoder #(parameter WIDTH = 8) (
   end
 endmodule
 
+module ppa_mux2_1 #(parameter WIDTH = 1) (
+  input  logic [WIDTH-1:0] d0, d1, 
+  input  logic             s, 
+  output logic [WIDTH-1:0] y);
+
+  assign y = s ? d1 : d0; 
+endmodule
+
+module ppa_mux4_1 #(parameter WIDTH = 1) (
+  input  logic [WIDTH-1:0] d0, d1, d2, d3,
+  input  logic [1:0]       s, 
+  output logic [WIDTH-1:0] y);
+
+  assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0); 
+endmodule
+
+module ppa_mux8_1 #(parameter WIDTH = 1) (
+  input  logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
+  input  logic [2:0]       s, 
+  output logic [WIDTH-1:0] y);
+
+  assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0)); 
+endmodule
+
 module ppa_mux2_8 #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] d0, d1, 
   input  logic             s,