mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Progress.
This commit is contained in:
Ross Thompson
parent
c8a5d61cbb
commit
a532eb61ba
@ -166,30 +166,29 @@ add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/WriteDataE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
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add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/ebu/BusState
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/NextBusState
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/ebu/AtomicMaskedM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/ebu/LSUBusSize
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRDATA
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITED
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/both
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/save
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/restore
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/dis
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add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/sel
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/NextBusState
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HCLK
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESETn
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HREADY
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESP
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HADDR
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWDATA
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWRITE
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HSIZE
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURST
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HPROT
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HADDRD
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add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HSIZED
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add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall
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@ -197,15 +196,11 @@ add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
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add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr
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add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
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add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/BusCurrState
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/RW
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/CacheRW
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/Cacheable
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUBusRead
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUBusWrite
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUBusAdr
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUBusAck
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUBusHRDATA
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUBusHWDATA
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add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
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@ -222,7 +217,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/LSUBusBuffer
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
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@ -311,13 +305,11 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
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add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/LSUBusBuffer
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
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@ -423,11 +415,8 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
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add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
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add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
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add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
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add wave -noupdate -group ifu -color Gold /testbench/dut/core/ifu/bus/busdp/busfsm/BusCurrState
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusRead
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAdr
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAck
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusHRDATA
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUTransComplete
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add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
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add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
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@ -443,7 +432,6 @@ add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and
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add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
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add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
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add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
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add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/LSUBusBuffer
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add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
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add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetDirtyWay
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add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetValidWay
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@ -512,8 +500,20 @@ add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I
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add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
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add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
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add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
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add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/BusCurrState
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/CacheRW
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/RW
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/HREADY
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/WordCount
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/FetchBuffer
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/CaptureEn
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/HADDR
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/HSIZE
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/HTRANS
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/CacheBusAck
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add wave -noupdate /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/WordCountFlag
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 2} {989221 ns} 1} {{Cursor 3} {999815 ns} 1} {{Cursor 4} {311315 ns} 0}
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WaveRestoreCursors {{Cursor 2} {989221 ns} 1} {{Cursor 3} {999815 ns} 1} {{Cursor 4} {2306 ns} 0}
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quietly wave cursor active 3
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 314
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@ -529,4 +529,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {311178 ns} {311464 ns}
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WaveRestoreZoom {2137 ns} {2477 ns}
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8
pipelined/src/cache/AHBBuscachefsm.sv
vendored
8
pipelined/src/cache/AHBBuscachefsm.sv
vendored
@ -96,7 +96,7 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
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.q(WordCountDelayed));
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assign NextWordCount = WordCount + 1'b1;
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assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0] ); // Detect when we are waiting on the final access.
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assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0] ); // Detect when we are waiting on the final access.
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assign WordCntEn = (BusNextState == STATE_CACHE_ACCESS & HREADY) |
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(BusNextState == STATE_READY & |CacheRW & HREADY);
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@ -128,10 +128,10 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
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assign BusCommitted = BusCurrState != STATE_READY; // *** might not be correct
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assign HTRANS = (BusCurrState == STATE_READY & HREADY & |RW) |
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assign HTRANS = (BusCurrState == STATE_READY & HREADY & (|RW | |CacheRW)) |
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(BusCurrState == STATE_CAPTURE & ~HREADY) |
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(BusCurrState == STATE_CACHE_ACCESS & ~HREADY & |WordCount) ? AHB_NONSEQ :
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(BusCurrState == STATE_CACHE_ACCESS & ~HREADY & ~|WordCount) ? AHB_SEQ : AHB_IDLE;
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(BusCurrState == STATE_CACHE_ACCESS) ? AHB_SEQ : AHB_IDLE;
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assign HWRITE = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) | // *** might not be necessary, maybe just RW[0]
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(BusCurrState == STATE_CACHE_ACCESS & CacheRW[0]);
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@ -152,7 +152,7 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
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(BusCurrState == STATE_CAPTURE) |
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(BusCurrState == STATE_DELAY);
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assign CacheBusAck = (BusCurrState == STATE_CAPTURE & HREADY & WordCountFlag);
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assign CacheBusAck = (BusCurrState == STATE_CACHE_ACCESS & HREADY & WordCountFlag);
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assign SelBusWord = (BusCurrState == STATE_READY & RW[0]) |
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(BusCurrState == STATE_CAPTURE & RW[0]) |
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3
pipelined/src/cache/cachefsm.sv
vendored
3
pipelined/src/cache/cachefsm.sv
vendored
@ -194,8 +194,9 @@ module cachefsm
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assign FlushAdrCntRst = (CurrState == STATE_READY);
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assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR);
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// Bus interface controls
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assign CacheFetchLine = (CurrState == STATE_READY & DoAnyMiss);
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assign CacheFetchLine = (CurrState == STATE_READY & DoAnyMiss) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck);
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assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) |
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(CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) |
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(CurrState == STATE_FLUSH_CHECK & VictimDirty);
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// **** can this be simplified?
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assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss.
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@ -231,17 +231,15 @@ module ifu (
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.NextAdr(PCNextFSpill[11:0]),
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.PAdr(PCPF),
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.CacheCommitted(), .InvalidateCache(InvalidateICacheM));
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cachedp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
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cachedp(.clk, .reset,
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.HRDATA(HRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelBusWord(),
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.BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .BusTransComplete(IFUTransComplete),
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.Funct3(3'b010), .HADDR(IFUHADDR), .CacheBusAdr(ICacheBusAdr),
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.WordCount(),
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.CacheFetchLine(ICacheFetchLine),
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.CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck),
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AHBCachedp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
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cachedp(.HCLK(clk), .HRESETn(~reset),
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.HRDATA,
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.CacheRW({ICacheFetchLine, 1'b0} & ~{ITLBMissF, ITLBMissF}), .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS),
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.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
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.WordCount(), .SelUncachedAdr, .SelBusWord(),
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.CacheBusAck(ICacheBusAck),
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.FetchBuffer, .PAdr(PCPF),
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.SelUncachedAdr,
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.IgnoreRequest(ITLBMissF), .RW(NonIROMMemRWM), .CPUBusy, .Cacheable(CacheableF),
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.RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF}), .CPUBusy, .Cacheable(CacheableF),
|
||||
.BusStall, .BusCommitted());
|
||||
|
||||
mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]),
|
||||
|
||||
@ -265,7 +265,7 @@ module lsu (
|
||||
.WordCount, .SelBusWord,
|
||||
.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheRW({DCacheFetchLine, DCacheWriteLine} & ~{IgnoreRequest, IgnoreRequest}),
|
||||
.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM),
|
||||
.SelUncachedAdr, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}), .CPUBusy, .Cacheable(CacheableM),
|
||||
.SelUncachedAdr, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableM, CacheableM}), .CPUBusy, .Cacheable(CacheableM),
|
||||
.BusStall, .BusCommitted(BusCommittedM));
|
||||
|
||||
mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user