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updated trap handler alignemnts to 64 bytes in priv tests

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Kip Macsai-Goren 2022-12-22 14:23:04 -08:00
parent 04bc787647
commit a37bde7452
4 changed files with 6 additions and 8 deletions
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3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
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@ -299,8 +299,7 @@ end_trap_triggers:
// -------------------------------------------------------------------------------------------- // --------------------------------------------------------------------------------------------
//.align 6 .align 6
.align 2
trap_handler_\MODE\(): trap_handler_\MODE\():
j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
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@ -35,8 +35,8 @@ RVTEST_CODE_BEGIN
# --------------------------------------------------------------------------------------------- # ---------------------------------------------------------------------------------------------
j main_code j main_code
# Thanks to MTVEC[1:0], trap handler addresses need to be aligned to a 4-byte boundary # 64 byte alignment for vectored traps to align with xtev
.align 2 .align 6
################### ###################
################### ###################
trap_handler: ##### trap_handler: #####

3
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
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@ -293,8 +293,7 @@ end_trap_triggers:
// //
// -------------------------------------------------------------------------------------------- // --------------------------------------------------------------------------------------------
//.align 6 .align 6
.align 3
trap_handler_\MODE\(): trap_handler_\MODE\():
j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S
View File

@ -35,8 +35,8 @@ RVTEST_CODE_BEGIN
# --------------------------------------------------------------------------------------------- # ---------------------------------------------------------------------------------------------
j main_code j main_code
# Thanks to MTVEC[1:0], trap handler addresses need to be aligned to a 4-byte boundary # 64 byte alignment for vectored traps to align with xtev
.align 2 .align 6
################### ###################
################### ###################
trap_handler: ##### trap_handler: #####