From a37bde745273ecd423053477c4bce6746ce555e1 Mon Sep 17 00:00:00 2001
From: Kip Macsai-Goren <kmacsaigoren@hmc.edu>
Date: Thu, 22 Dec 2022 14:23:04 -0800
Subject: [PATCH] updated trap handler alignemnts to 64 bytes in priv tests

---
 .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h                 | 3 +--
 .../riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S  | 4 ++--
 .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h                 | 3 +--
 .../riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S  | 4 ++--
 4 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
index 7dfe1f0a3..07813da16 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
@@ -299,8 +299,7 @@ end_trap_triggers:
     // --------------------------------------------------------------------------------------------
 
 
-//.align 6
-.align 2
+.align 6
 trap_handler_\MODE\():
     j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
     // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
index 46e2483d5..febab70ef 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
@@ -35,8 +35,8 @@ RVTEST_CODE_BEGIN
 
     # ---------------------------------------------------------------------------------------------
     j main_code
-# Thanks to MTVEC[1:0], trap handler addresses need to be aligned to a 4-byte boundary
-.align 2
+# 64 byte alignment for vectored traps to align with xtev
+.align 6
 ###################
 ###################
 trap_handler: #####
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
index 7310857ab..86568c12b 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
@@ -293,8 +293,7 @@ end_trap_triggers:
     //     
     // --------------------------------------------------------------------------------------------
 
-//.align 6
-.align 3
+.align 6
 trap_handler_\MODE\():
     j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
     // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S
index c4e5a96e6..69562c59d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S
@@ -35,8 +35,8 @@ RVTEST_CODE_BEGIN
 
     # ---------------------------------------------------------------------------------------------
     j main_code
-# Thanks to MTVEC[1:0], trap handler addresses need to be aligned to a 4-byte boundary
-.align 2
+# 64 byte alignment for vectored traps to align with xtev
+.align 6
 ###################
 ###################
 trap_handler: #####