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Refactored IEU/ALU logic

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This commit is contained in:
David Harris 2021-12-08 13:48:04 -08:00
parent e14eb9872e
commit a1f8f7babe
3 changed files with 5 additions and 11 deletions
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2
wally-pipelined/src/ieu/controller.sv
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@ -173,7 +173,7 @@ module controller(
assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);
assign sraD = (Funct3D == 3'b101 & Funct7D[5]); assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
assign SubArithD = subD | sraD | sltD | sltuD; // TRUE for R-type subtracts and sra, slt, sltu assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu
// assign SubArithD = aluc3D; // ***cleanup // assign SubArithD = aluc3D; // ***cleanup
// *** replace all of this // *** replace all of this

7
wally-pipelined/src/ieu/datapath.sv
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@ -111,14 +111,9 @@ module datapath (
mux3 #(`XLEN) fbemux(RD2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE); mux3 #(`XLEN) fbemux(RD2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE);
mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE); mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
// mux2 #(`XLEN) srcamux2(SrcAE, PCLinkE, JumpE, SrcAE2);
mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
// mux2 #(`XLEN) srcbmux2(SrcBE, {`XLEN{1'b0}}, JumpE, SrcBE2); // *** May be able to remove this mux. alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUPreResultE, AddressE);
alu #(`XLEN) alu(SrcAE/*SrcAE2*/, SrcBE/*SrcBE2*/, ALUControlE, Funct3E, ALUPreResultE, AddressE /*, FlagsE */);
// redo ALUControlE to simplify - jus needs ALUAddE, Funct3E, W64E
comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE); comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
// mux2 #(`XLEN) targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE); // *** PCE alsready should be selectable for SrcAE
// assign PCTargetE = ExtImmE + TargetBaseE;
mux2 #(`XLEN) altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE);
mux2 #(`XLEN) aluresultmux(ALUPreResultE, AltResultE, ALUResultSrcE, ALUResultE); mux2 #(`XLEN) aluresultmux(ALUPreResultE, AltResultE, ALUResultSrcE, ALUResultE);

7
wally-pipelined/src/ieu/ieu.sv
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@ -99,7 +99,7 @@ module ieu (
.StallE, .FlushE, .FlagsE, .StallE, .FlushE, .FlagsE,
.PCSrcE, // for datapath and Hazard Unit .PCSrcE, // for datapath and Hazard Unit
.ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUControlE, .ALUSrcAE, .ALUSrcBE,
.TargetSrcE, .ALUResultSrcE,
.MemReadE, .CSRReadE, // for Hazard Unit .MemReadE, .CSRReadE, // for Hazard Unit
.Funct3E, .MulDivE, .W64E, .Funct3E, .MulDivE, .W64E,
.JumpE, .JumpE,
@ -124,12 +124,11 @@ module ieu (
.ImmSrcD, .InstrD, .ImmSrcD, .InstrD,
// Execute stage signals // Execute stage signals
.StallE, .FlushE, .ForwardAE, .ForwardBE, .StallE, .FlushE, .ForwardAE, .ForwardBE,
.ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE,
.TargetSrcE, .JumpE, .IllegalFPUInstrE, .ALUResultSrcE, .JumpE, .IllegalFPUInstrE,
.FWriteDataE, .PCE, .PCLinkE, .FlagsE, .FWriteDataE, .PCE, .PCLinkE, .FlagsE,
.PCTargetE, .PCTargetE,
.ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
.SrcAE, .SrcBE,
// Memory stage signals // Memory stage signals
.StallM, .FlushM, .FWriteIntM, .FIntResM, .StallM, .FlushM, .FWriteIntM, .FIntResM,
.SrcAM, .WriteDataM, .MemAdrM, .MemAdrE, .SrcAM, .WriteDataM, .MemAdrM, .MemAdrE,