diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv
index 97ffda481..90ab5af60 100644
--- a/wally-pipelined/src/ieu/controller.sv
+++ b/wally-pipelined/src/ieu/controller.sv
@@ -173,7 +173,7 @@ module controller(
   assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);
   assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
 
-  assign SubArithD = subD | sraD | sltD | sltuD; // TRUE for R-type subtracts and sra, slt, sltu
+  assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu
 //  assign SubArithD = aluc3D; // ***cleanup
 
   // *** replace all of this
diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index 9070d2d15..b0645f810 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -111,14 +111,9 @@ module datapath (
   mux3  #(`XLEN)  fbemux(RD2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE);
   mux2  #(`XLEN)  writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
   mux2  #(`XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
-//  mux2  #(`XLEN)  srcamux2(SrcAE, PCLinkE, JumpE, SrcAE2);  
   mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
-//  mux2  #(`XLEN)  srcbmux2(SrcBE, {`XLEN{1'b0}}, JumpE, SrcBE2); // *** May be able to remove this mux.
-  alu   #(`XLEN)  alu(SrcAE/*SrcAE2*/, SrcBE/*SrcBE2*/, ALUControlE, Funct3E, ALUPreResultE, AddressE /*, FlagsE */);
-  // redo ALUControlE to simplify - jus needs ALUAddE, Funct3E, W64E
+  alu   #(`XLEN)  alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUPreResultE, AddressE);
   comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
-//  mux2  #(`XLEN)  targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE); // *** PCE alsready should be selectable for SrcAE
-//  assign  PCTargetE = ExtImmE + TargetBaseE;
   mux2 #(`XLEN) altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE);
   mux2 #(`XLEN) aluresultmux(ALUPreResultE, AltResultE, ALUResultSrcE, ALUResultE);
 
diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv
index 9d2c3aceb..4619b337c 100644
--- a/wally-pipelined/src/ieu/ieu.sv
+++ b/wally-pipelined/src/ieu/ieu.sv
@@ -99,7 +99,7 @@ module ieu (
     .StallE, .FlushE, .FlagsE, 
     .PCSrcE,        // for datapath and Hazard Unit
     .ALUControlE, .ALUSrcAE, .ALUSrcBE,
-    .TargetSrcE,
+    .ALUResultSrcE,
     .MemReadE, .CSRReadE, // for Hazard Unit
     .Funct3E, .MulDivE, .W64E,
     .JumpE,	
@@ -124,12 +124,11 @@ module ieu (
     .ImmSrcD, .InstrD,
     // Execute stage signals
     .StallE, .FlushE, .ForwardAE, .ForwardBE,
-    .ALUControlE, .ALUSrcAE, .ALUSrcBE,
-    .TargetSrcE, .JumpE, .IllegalFPUInstrE,
+    .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE,
+    .ALUResultSrcE, .JumpE, .IllegalFPUInstrE,
     .FWriteDataE, .PCE, .PCLinkE, .FlagsE,
     .PCTargetE,
     .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
-    .SrcAE, .SrcBE,
     // Memory stage signals
     .StallM, .FlushM, .FWriteIntM, .FIntResM, 
     .SrcAM, .WriteDataM, .MemAdrM, .MemAdrE,