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Removed logic from Verilog wrapper.

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This commit is contained in:
Ross Thompson 2022-08-21 14:07:43 -05:00
parent dad6770fc3
commit a049f456e8
1 changed files with 1 additions and 1 deletions
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pipelined/src/wally/wallypipelinedsocwrapper.v
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@ -42,7 +42,7 @@ module wallypipelinedsocwrapper (
output HCLK, HRESETn, output HCLK, HRESETn,
output [31:0] HADDR, output [31:0] HADDR,
output [`AHBW-1:0] HWDATA, output [`AHBW-1:0] HWDATA,
output logic [`XLEN/8-1:0] HWSTRB, output [`XLEN/8-1:0] HWSTRB,
output HWRITE, output HWRITE,
output [2:0] HSIZE, output [2:0] HSIZE,
output [2:0] HBURST, output [2:0] HBURST,