From a049f456e8ae8bd7ff45a9a1a39a51bb066b8220 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 21 Aug 2022 14:07:43 -0500 Subject: [PATCH] Removed logic from Verilog wrapper. --- pipelined/src/wally/wallypipelinedsocwrapper.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/wally/wallypipelinedsocwrapper.v b/pipelined/src/wally/wallypipelinedsocwrapper.v index 2a25f476f..faf762285 100644 --- a/pipelined/src/wally/wallypipelinedsocwrapper.v +++ b/pipelined/src/wally/wallypipelinedsocwrapper.v @@ -42,7 +42,7 @@ module wallypipelinedsocwrapper ( output HCLK, HRESETn, output [31:0] HADDR, output [`AHBW-1:0] HWDATA, - output logic [`XLEN/8-1:0] HWSTRB, + output [`XLEN/8-1:0] HWSTRB, output HWRITE, output [2:0] HSIZE, output [2:0] HBURST,