Merge branch 'main' into wsim_verilator

.gitignore

@@ -198,3 +198,6 @@ sim/verilator/wkdir
 sim/vcs/logs
 sim/vcs/wkdir
 benchmarks/coremark/coremark_results.csv
+fpga/zsbl/OBJ/*
+fpga/zsbl/bin/*
+sim/*.svg

fpga/zsbl/linker.x

@@ -0,0 +1,244 @@
+OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv",
+	      "elf64-littleriscv")
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib");
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  /* init segment to ensure we get a consistent start routine*/
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+  . = ALIGN(0x0); 
+  .init : {  
+  	*(.init) 
+  } 
+  _start_end = .;
+  
+  PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x0)); . = SEGMENT_START("text-segment", _start_end);
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+  .gnu.version_r  : { *(.gnu.version_r) }
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+      PROVIDE_HIDDEN (__rela_iplt_end = .);
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+    *(.gnu.warning)
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+    KEEP (*(SORT_NONE(.fini)))
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+     the same address within the page on the next page up.  */
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+     PROVIDE_HIDDEN (__tdata_start = .);
+     *(.tdata .tdata.* .gnu.linkonce.td.*)
+   }
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+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
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+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  }
+  .fini_array    :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  }
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
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+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .jcr            : { KEEP (*(.jcr)) }
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+  .data           :
+  {
+    __DATA_BEGIN__ = .;
+    *(.data .data.* .gnu.linkonce.d.*)
+    SORT(CONSTRUCTORS)
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+      .bss section disappears because there are no input sections.
+      FIXME: Why do we need it? When there is no .bss section, we do not
+      pad the .data section.  */
+   . = ALIGN(. != 0 ? 64 / 8 : 1);
+  }
+  . = ALIGN(64 / 8);
+  . = SEGMENT_START("ldata-segment", .);
+  . = ALIGN(64 / 8);
+  __BSS_END__ = .;
+    __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,
+		            MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
+  _end = .; PROVIDE (end = .);
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+  /* Stabs debugging sections.  */
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+     Symbols in the DWARF debugging sections are relative to the beginning
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+  /* GNU DWARF 1 extensions */
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+  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}

linux/buildroot-config-src/buildroot-2023.05.1/main.config

@@ -134,7 +134,7 @@ BR2_GCC_VERSION_12_X=y
 BR2_GCC_VERSION="12.3.0"
 BR2_EXTRA_GCC_CONFIG_OPTIONS=""
 BR2_TOOLCHAIN_BUILDROOT_CXX=y
-# BR2_TOOLCHAIN_BUILDROOT_FORTRAN is not set
+BR2_TOOLCHAIN_BUILDROOT_FORTRAN=y
 # BR2_GCC_ENABLE_OPENMP is not set
 # BR2_GCC_ENABLE_GRAPHITE is not set
 BR2_PACKAGE_HOST_GDB_ARCH_SUPPORTS=y
@@ -152,6 +152,7 @@ BR2_TOOLCHAIN_SUPPORTS_VARIADIC_MI_THUNK=y
 BR2_USE_WCHAR=y
 BR2_ENABLE_LOCALE=y
 BR2_INSTALL_LIBSTDCPP=y
+BR2_TOOLCHAIN_HAS_FORTRAN=y
 BR2_TOOLCHAIN_HAS_THREADS=y
 BR2_TOOLCHAIN_HAS_THREADS_DEBUG=y
 BR2_TOOLCHAIN_HAS_THREADS_NPTL=y
@@ -1086,10 +1087,6 @@ BR2_PACKAGE_PROVIDES_HOST_LUAINTERPRETER="host-lua"
 # BR2_PACKAGE_MICROPYTHON is not set
 # BR2_PACKAGE_MOARVM is not set
 BR2_PACKAGE_HOST_MONO_ARCH_SUPPORTS=y
-
-#
-# octave needs a toolchain w/ C++ and fortran, gcc >= 4.8
-#
 BR2_PACKAGE_HOST_OPENJDK_BIN_ARCH_SUPPORTS=y
 # BR2_PACKAGE_PERL is not set
 BR2_PACKAGE_PHP_ARCH_SUPPORTS=y
@@ -1731,10 +1728,7 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y
 # BR2_PACKAGE_ACE is not set
 # BR2_PACKAGE_APR is not set
 # BR2_PACKAGE_APR_UTIL is not set
-
+# BR2_PACKAGE_ARMADILLO is not set
-#
-# armadillo needs a toolchain w/ fortran, C++
-#
 # BR2_PACKAGE_ATF is not set
 # BR2_PACKAGE_AVRO_C is not set
 # BR2_PACKAGE_BCTOOLBOX is not set
@@ -1782,10 +1776,7 @@ BR2_PACKAGE_GOBJECT_INTROSPECTION_ARCH_SUPPORTS=y
 BR2_PACKAGE_JEMALLOC_ARCH_SUPPORTS=y
 # BR2_PACKAGE_JEMALLOC is not set
 BR2_PACKAGE_LAPACK_ARCH_SUPPORTS=y
-
+# BR2_PACKAGE_LAPACK is not set
-#
-# lapack/blas needs a toolchain w/ fortran
-#
 BR2_PACKAGE_LIBABSEIL_CPP_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBABSEIL_CPP is not set
 # BR2_PACKAGE_LIBARGTABLE2 is not set

sim/questa/run-imperas-linux.sh

@@ -7,4 +7,4 @@ export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100"
 #export OTHERFLAGS="+TRACE2LOG_ENABLE=1  +TRACE2LOG_AFTER=10500000"
 #export OTHERFLAGS=""
 
-vsim -c -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0"
+vsim -c -do "do questa/wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0"

src/uncore/uart_apb.sv

@@ -60,7 +60,7 @@ module uart_apb import cvw::*; #(parameter cvw_t P) (
   else              assign PRDATA = {Dout, Dout, Dout, Dout};   
   
   logic BAUDOUTb;  // loop tx clock BAUDOUTb back to rx clock RCLK
-  uartPC16550D #(P.UART_PRESCALE) u(  
+  uartPC16550D #(P.UART_PRESCALE) uartPC(  
     // Processor Interface
     .PCLK, .PRESETn,
     .A(entry), .Din, 

src/uncore/uncore.sv

@@ -139,7 +139,7 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   end else begin : gpio
     assign GPIOOUT = 0; assign GPIOEN = 0; assign GPIOIntr = 0;
   end
-  if (P.UART_SUPPORTED == 1) begin : uart
+  if (P.UART_SUPPORTED == 1) begin : uartgen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769
     uart_apb #(P) uart(
       .PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
       .PRDATA(PRDATA[3]), .PREADY(PREADY[3]), 

src/wally/wallypipelinedsoc.sv

@@ -79,7 +79,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
    );
 
   // instantiate uncore if a bus interface exists
-  if (P.BUS_SUPPORTED) begin : uncore
+  if (P.BUS_SUPPORTED) begin : uncoregen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769
     uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK,
       .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
       .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC,

testbench/testbench.sv

@@ -443,10 +443,10 @@ module testbench;
         string romfilename, sdcfilename;
         romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
         sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
-        //$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
+        //$readmemh(romfilename, dut.uncoregen.uncore.bootrom.bootrom.memory.ROM);
         //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
         // shorten sdc timers for simulation
-        //dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
+        //dut.uncoregen.uncore.sdc.SDC.LimitTimers = 1;
       end
     end
   end else if (P.IROM_SUPPORTED) begin
@@ -460,13 +460,13 @@ module testbench;
       if (LoadMem) begin
         if (TEST == "buildroot") begin
           memFile = $fopen(bootmemfilename, "rb");
-          readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM, memFile);
+          readResult = $fread(dut.uncoregen.uncore.bootrom.bootrom.memory.ROM, memFile);
           $fclose(memFile);
           memFile = $fopen(memfilename, "rb");
-          readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM, memFile);
+          readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.RAM, memFile);
           $fclose(memFile);
         end else 
-          $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+          $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.RAM);
         if (TEST == "embench") $display("Read memfile %s", memfilename);
       end
       if (CopyRAM) begin
@@ -475,7 +475,7 @@ module testbench;
         EndIndex = (end_signature_addr >> LogXLEN) + 8;
         BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
         for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
-          testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncore.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex];
+          testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncoregen.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex];
         end
       end
     end
@@ -503,7 +503,7 @@ module testbench;
     always @(posedge clk) 
       if (ResetMem)  // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory)
         for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) 
-          dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = 0;
+          dut.uncoregen.uncore.ram.ram.memory.RAM[adrindex] = 0;
 
   ////////////////////////////////////////////////////////////////////////////////
   // Actual hardware
@@ -594,15 +594,17 @@ module testbench;
   end
 
   // Append UART output to file for tests
+  if (P.UART_SUPPORTED) begin: uart_logger
     always @(posedge clk) begin
-    if (P.UART_SUPPORTED & TEST == "buildroot") begin
+      if (TEST == "buildroot") begin
-      if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin
+        if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin
           memFile = $fopen(uartoutfilename, "ab");
-        $fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din);
+          $fwrite(memFile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din);
           $fclose(memFile);
         end
       end
     end
+  end
 
   // Termination condition
   // terminate on a specific ECALL after li x3,1 for old Imperas tests,  *** remove this when old imperas tests are removed
@@ -875,8 +877,10 @@ end
       // **************************************
       // ***** BUG BUG BUG make sure RT undoes this.
       //if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
-      //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
+
-      //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
+      //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncoregen.uncore.ram.ram.memory.RAM[testadrNoBase+i];
+      if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncoregen.uncore.ram.ram.memory.RAM[testadrNoBase+i];
+      //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncoregen.uncore.ram.ram.memory.RAM[testadrNoBase+i];
       //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
       //if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin
       if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin