From 9f60256f22e0f71389498da2f06f1faaad2b46f2 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 24 Mar 2022 17:08:10 -0700 Subject: [PATCH] 1st attempt at multiple channel PLIC --- linux/testvector-generation/genCheckpoint.sh | 6 +- linux/testvector-generation/parsePlicState.py | 24 +- pipelined/src/privileged/csr.sv | 14 +- pipelined/src/privileged/csri.sv | 30 +- pipelined/src/privileged/privileged.sv | 4 +- pipelined/src/uncore/plic.sv | 229 +++++++++------ pipelined/src/uncore/uncore.sv | 5 +- pipelined/src/wally/wallypipelinedcore.sv | 268 +++++++++--------- pipelined/src/wally/wallypipelinedsoc.sv | 6 +- pipelined/testbench/testbench-linux.sv | 4 +- 10 files changed, 325 insertions(+), 265 deletions(-) diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh index 8f4d0a111..dea4d5551 100755 --- a/linux/testvector-generation/genCheckpoint.sh +++ b/linux/testvector-generation/genCheckpoint.sh @@ -101,10 +101,12 @@ then set logging on # Priority Levels for sources 1 thru 63 x/63xw 0x0C000004 - # Interrupt Enables + # Interrupt Enables for sources 1 thru 63 for contexts 0 and 1 x/2xw 0x0C020000 - # Global Priority Threshold + x/2xw 0x0C020080 + # Global Priority Threshold for contexts 0 and 1 x/1xw 0x0C200000 + x/1xw 0x0C201000 set logging off shell echo \"GDB storing RAM to $rawRamFile\" dump binary memory $rawRamFile 0x80000000 0xffffffff diff --git a/linux/testvector-generation/parsePlicState.py b/linux/testvector-generation/parsePlicState.py index a3c3787c8..35ef00b1d 100755 --- a/linux/testvector-generation/parsePlicState.py +++ b/linux/testvector-generation/parsePlicState.py @@ -1,5 +1,6 @@ #! /usr/bin/python3 import sys, os +from functools import reduce ################ # Helper Funcs # @@ -21,6 +22,9 @@ def tokenize(string): token = token + char return tokens +def strip0x(num): + return num[2:] + def stripZeroes(num): num = num.strip('0') if num=='': @@ -42,7 +46,7 @@ if not os.path.exists(rawPlicStateFile): sys.exit('Error input file '+rawPlicStateFile+'not found') with open(rawPlicStateFile, 'r') as rawPlicStateFile: - plicIntPriorityArray=[] + plicIntPriorityArray = [] # iterates over number of different sources # 0x0C000004 thru 0x0C000010 plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] # 0x0C000014 thru 0x0C000020 @@ -76,20 +80,30 @@ with open(rawPlicStateFile, 'r') as rawPlicStateFile: # 0x0C0000f4 thru 0x0C0000fc plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:] + plicIntEnableArray = [] # iterates over number of different contexts # 0x0C020000 thru 0x0C020004 plicIntEnable = tokenize(rawPlicStateFile.readline())[1:] + plicIntEnable = map(strip0x,plicIntEnable) + plicIntEnableArray.append(reduce(lambda x,y: x+y,plicIntEnable)) + # 0x0C020080 thru 0x0C020084 + plicIntEnable = tokenize(rawPlicStateFile.readline())[1:] + plicIntEnable = map(strip0x,plicIntEnable) + plicIntEnableArray.append(reduce(lambda x,y: x+y,plicIntEnable)) + plicIntPriorityThresholdArray = [] # iterates over number of different contexts # 0x0C200000 - plicIntPriorityThreshold = tokenize(rawPlicStateFile.readline())[1:] + plicIntPriorityThresholdArray += tokenize(rawPlicStateFile.readline())[1:] + # 0x0C201000 + plicIntPriorityThresholdArray += tokenize(rawPlicStateFile.readline())[1:] with open(outDir+'checkpoint-PLIC_INT_PRIORITY', 'w') as outFile: for word in plicIntPriorityArray: outFile.write(stripZeroes(word[2:])+'\n') with open(outDir+'checkpoint-PLIC_INT_ENABLE', 'w') as outFile: - for word in plicIntEnable: - outFile.write(stripZeroes(word[2:])) + for word in plicIntEnableArray: + outFile.write(word+'\n') with open(outDir+'checkpoint-PLIC_THRESHOLD', 'w') as outFile: - for word in plicIntPriorityThreshold: + for word in plicIntPriorityThresholdArray: outFile.write(stripZeroes(word[2:])+'\n') print("Finished parsing PLIC state!") diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index cac7aa670..ecdcbe50d 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -43,13 +43,13 @@ module csr #(parameter input logic [31:0] InstrM, input logic [`XLEN-1:0] PCM, SrcAM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, - input logic TimerIntM, ExtIntM, SwIntM, + input logic TimerIntM, ExtIntM, ExtIntS, SwIntM, input logic [63:0] MTIME_CLINT, input logic InstrValidM, FRegWriteM, LoadStallD, - input logic BPPredDirWrongM, - input logic BTBPredPCWrongM, - input logic RASPredPCWrongM, - input logic BPPredClassNonCFIWrongM, + input logic BPPredDirWrongM, + input logic BTBPredPCWrongM, + input logic RASPredPCWrongM, + input logic BPPredClassNonCFIWrongM, input logic [4:0] InstrClassM, input logic DCacheMiss, input logic DCacheAccess, @@ -123,7 +123,7 @@ module csr #(parameter assign CSRUWriteM = CSRWriteM; csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRMWriteM, .CSRSWriteM, - .CSRAdrM, .ExtIntM, .TimerIntM, .SwIntM, + .CSRAdrM, .ExtIntM, .ExtIntS, .TimerIntM, .SwIntM, .MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM); csrsr csrsr(.clk, .reset, .StallW, .WriteMSTATUSM, .WriteSSTATUSM, @@ -167,7 +167,7 @@ module csr #(parameter // merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 & PrivilegeModeW != `M_MODE) | - (CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == `U_MODE); + (CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == `U_MODE); assign IllegalCSRAccessM = ((IllegalCSRCAccessM & IllegalCSRMAccessM & IllegalCSRSAccessM & IllegalCSRUAccessM | InsufficientCSRPrivilegeM) & CSRReadM) | IllegalCSRMWriteReadonlyM; diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 8a3f42fdf..7eff94962 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -41,7 +41,7 @@ module csri #(parameter input logic InstrValidNotFlushedM, StallW, input logic CSRMWriteM, CSRSWriteM, input logic [11:0] CSRAdrM, - input logic ExtIntM, TimerIntM, SwIntM, + input logic ExtIntM, ExtIntS, TimerIntM, SwIntM, input logic [`XLEN-1:0] MIDELEG_REGW, output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, input logic [`XLEN-1:0] CSRWriteValM @@ -57,12 +57,12 @@ module csri #(parameter always_comb begin IntInM = 0; - IntInM[11] = ExtIntM;; // MEIP - IntInM[9] = ExtIntM & MIDELEG_REGW[9]; // SEIP - IntInM[7] = TimerIntM; // MTIP - IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP - IntInM[3] = SwIntM; // MSIP - IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP + IntInM[11] = ExtIntM; // MEIP + IntInM[9] = ExtIntS | (ExtIntM & MIDELEG_REGW[9]); // SEIP + IntInM[7] = TimerIntM; // MTIP + IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP + IntInM[3] = SwIntM; // MSIP + IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP end // Interrupt Write Enables @@ -82,21 +82,19 @@ module csri #(parameter assign MIP_WRITE_MASK = 12'h000; assign SIP_WRITE_MASK = 12'h000; end - always @(posedge clk) //, posedge reset) begin // *** I strongly feel that IntInM should go directly to IP_REGW -- Ben 9/7/21 + always @(posedge clk) if (reset) IP_REGW_writeable <= 10'b0; - else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable - else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable -// else if (WriteUIPM) IP_REGW = (CSRWriteValM & 12'hBBB) | (NextIPM & 12'h080); // MTIP unclearable - else IP_REGW_writeable <= IP_REGW_writeable | IntInM[9:0]; // *** check this turns off interrupts properly even when MIDELEG changes - always @(posedge clk) //, posedge reset) begin + else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | {1'b0,IntInM[8:0]}; // MTIP unclearable + else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | {1'b0,IntInM[8:0]}; // MTIP unclearable + else IP_REGW_writeable <= IP_REGW_writeable | {1'b0, IntInM[8:0]}; // *** check this turns off interrupts properly even when MIDELEG changes + always @(posedge clk) if (reset) IE_REGW <= 12'b0; else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'hAAA); // MIE controls M and S fields else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields -// else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field // restricted views of registers - // Add MEIP read-only signal - assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable}; + // Add ExtIntM read-only signal + assign IP_REGW = {ExtIntM,1'b0,ExtIntS,9'b0} | {2'b0,IP_REGW_writeable}; // Machine Mode assign MIP_REGW = IP_REGW; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 8493a15bd..9a8fb9f8a 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -55,7 +55,7 @@ module privileged ( input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD, input logic LoadMisalignedFaultM, input logic StoreAmoMisalignedFaultM, - input logic TimerIntM, ExtIntM, SwIntM, + input logic TimerIntM, ExtIntM, ExtIntS, SwIntM, input logic [63:0] MTIME_CLINT, input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM, input logic [4:0] SetFflagsM, @@ -150,7 +150,7 @@ module privileged ( .StallE, .StallM, .StallW, .InstrM, .PCM, .SrcAM, .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, - .TimerIntM, .ExtIntM, .SwIntM, + .TimerIntM, .ExtIntM, .ExtIntS, .SwIntM, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, diff --git a/pipelined/src/uncore/plic.sv b/pipelined/src/uncore/plic.sv index 2d5459989..cccbe75cf 100644 --- a/pipelined/src/uncore/plic.sv +++ b/pipelined/src/uncore/plic.sv @@ -37,6 +37,15 @@ `include "wally-config.vh" +`define N `PLIC_NUM_SRC +// number of interrupt sources +// does not include source 0, which does not connect to anything according to spec +// up to 63 sources supported; *** in the future, allow up to 1023 sources + +`define C 2 +// number of conexts +// hardcoded to 2 contexts for now; *** later upgrade to arbitrary (up to 15872) contexts + module plic ( input logic HCLK, HRESETn, input logic HSELPLIC, @@ -48,25 +57,26 @@ module plic ( input logic UARTIntr,GPIOIntr, output logic [`XLEN-1:0] HREADPLIC, output logic HRESPPLIC, HREADYPLIC, - output logic ExtIntM); - - localparam N=`PLIC_NUM_SRC; // should not exceed 63; does not inlcude source 0, which does not connect to anything according to spec + output logic ExtIntM, ExtIntS); logic memwrite, memread, initTrans; logic [23:0] entry, entryd; logic [31:0] Din, Dout; - logic [N:1] requests; - logic [2:0] intPriority[N:1]; - logic [2:0] intThreshold; - logic [N:1] intPending, nextIntPending, intEn, intInProgress; - logic [5:0] intClaim; // ID's are 6 bits if we stay within 63 sources - - logic [N:1] pendingArray[7:1]; - logic [7:1] pendingPGrouped; - logic [7:1] pendingMaxP; - logic [N:1] pendingRequestsAtMaxP; - logic [7:1] threshMask; + // context-independent signals + logic [`N:1] requests; + logic [`N:1][2:0] intPriority; + logic [`N:1] intInProgress, intPending, nextIntPending; + + // context-dependent signals + logic [`C-1:0][2:0] intThreshold; + logic [`C-1:0][`N:1] intEn; + logic [`C-1:0][5:0] intClaim; // ID's are 6 bits if we stay within 63 sources + logic [`C-1:0][7:1][`N:1] irqMatrix; + logic [`C-1:0][7:1] priorities_with_irqs; + logic [`C-1:0][7:1] max_priority_with_irqs; + logic [`C-1:0][`N:1] irqs_at_max_priority; + logic [`C-1:0][7:1] threshMask; // ======= // AHB I/O @@ -82,12 +92,12 @@ module plic ( // account for subword read/write circuitry // -- Note PLIC registers are 32 bits no matter what; access them with LW SW. - if (`XLEN == 64) begin + if (`XLEN == 64) begin assign Din = entryd[2] ? HWDATA[63:32] : HWDATA[31:0]; assign HREADPLIC = entryd[2] ? {Dout,32'b0} : {32'b0,Dout}; end else begin // 32-bit - assign Din = HWDATA[31:0]; assign HREADPLIC = Dout; + assign Din = HWDATA[31:0]; end // ================== @@ -96,43 +106,56 @@ module plic ( always @(posedge HCLK,negedge HRESETn) begin // resetting if (~HRESETn) begin - intPriority <= #1 '{default:3'b0}; - intEn <= #1 {N{1'b0}}; - intThreshold <= #1 3'b0; - intInProgress <= #1 {N{1'b0}}; + intPriority <= #1 {`N{3'b0}}; + intEn <= #1 {2{`N'b0}}; + intThreshold <= #1 {2{3'b0}}; + intInProgress <= #1 `N'b0; // writing end else begin if (memwrite) casez(entryd) 24'h0000??: intPriority[entryd[7:2]] <= #1 Din[2:0]; - `ifdef PLIC_NUM_SRC_LT_32 - 24'h002000: intEn[N:1] <= #1 Din[N:1]; + `ifdef PLIC_NUM_SRC_LT_32 // *** switch to a generate for loop so as to deprecate PLIC_NUM_SRC_LT_32 and allow up to 1023 sources + 24'h002000: intEn[0][`N:1] <= #1 Din[`N:1]; + 24'h002080: intEn[1][`N:1] <= #1 Din[`N:1]; `endif `ifndef PLIC_NUM_SRC_LT_32 - 24'h002000: intEn[31:1] <= #1 Din[31:1]; - 24'h002004: intEn[N:32] <= #1 Din[31:0]; + 24'h002000: intEn[0][31:1] <= #1 Din[31:1]; + 24'h002004: intEn[0][`N:32] <= #1 Din[31:0]; + 24'h002080: intEn[1][31:1] <= #1 Din[31:1]; + 24'h002084: intEn[1][`N:32] <= #1 Din[31:0]; `endif - 24'h200000: intThreshold[2:0] <= #1 Din[2:0]; - 24'h200004: intInProgress <= #1 intInProgress & ~(`PLIC_NUM_SRC'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion + 24'h200000: intThreshold[0] <= #1 Din[2:0]; + 24'h200004: intInProgress <= #1 intInProgress & ~(`N'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion + 24'h201000: intThreshold[1] <= #1 Din[2:0]; + 24'h201004: intInProgress <= #1 intInProgress & ~(`N'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion endcase // reading if (memread) casez(entry) 24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]}; `ifdef PLIC_NUM_SRC_LT_32 - 24'h001000: Dout <= #1 {{(31-N){1'b0}},intPending[N:1],1'b0}; - 24'h002000: Dout <= #1 {{(31-N){1'b0}},intEn[N:1],1'b0}; + 24'h001000: Dout <= #1 {{(31-`N){1'b0}},intPending,1'b0}; + 24'h002000: Dout <= #1 {{(31-`N){1'b0}},intEn[0],1'b0}; + 24'h002080: Dout <= #1 {{(31-`N){1'b0}},intEn[1],1'b0}; `endif `ifndef PLIC_NUM_SRC_LT_32 24'h001000: Dout <= #1 {intPending[31:1],1'b0}; - 24'h001004: Dout <= #1 {{(63-N){1'b0}},intPending[N:32]}; - 24'h002000: Dout <= #1 {intEn[31:1],1'b0}; - 24'h002004: Dout <= #1 {{(63-N){1'b0}},intEn[N:32]}; + 24'h001004: Dout <= #1 {{(63-`N){1'b0}},intPending[`N:32]}; + 24'h002000: Dout <= #1 {intEn[0][31:1],1'b0}; + 24'h002004: Dout <= #1 {{(63-`N){1'b0}},intEn[0][`N:32]}; + 24'h002080: Dout <= #1 {intEn[0][31:1],1'b0}; + 24'h002084: Dout <= #1 {{(63-`N){1'b0}},intEn[1][`N:32]}; `endif - 24'h200000: Dout <= #1 {29'b0,intThreshold[2:0]}; + 24'h200000: Dout <= #1 {29'b0,intThreshold[0]}; 24'h200004: begin - Dout <= #1 {26'b0,intClaim}; - intInProgress <= #1 intInProgress | (`PLIC_NUM_SRC'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed + Dout <= #1 {26'b0,intClaim[0]}; + intInProgress <= #1 intInProgress | (`N'b1 << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed + end + 24'h201000: Dout <= #1 {29'b0,intThreshold[1]}; + 24'h201004: begin + Dout <= #1 {26'b0,intClaim[1]}; + intInProgress <= #1 intInProgress | (`N'b1 << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed end default: Dout <= #1 32'h0; // invalid access endcase @@ -143,7 +166,7 @@ module plic ( // connect sources to requests always_comb begin - requests = {N{1'b0}}; + requests = `N'b0; `ifdef PLIC_GPIO_ID requests[`PLIC_GPIO_ID] = GPIOIntr; `endif @@ -152,66 +175,88 @@ module plic ( `endif end - // pending updates - // *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered) - assign nextIntPending = (intPending | (requests & ~intInProgress)) & // requests should raise intPending except when their service routine is already in progress - ~({N{((entry == 24'h200004) & memread)}} << (intClaim-1)); // clear pending bit when claim register is read - flopr #(N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending); + // pending interrupt requests + assign nextIntPending = + (intPending | // existing pending requests + (requests & ~intInProgress)) & // assert new requests (if they aren't already being serviced) + ~({`N{((entry == 24'h200004) & memread)}} << (intClaim[0]-1)) & // deassert requests that just completed + ~({`N{((entry == 24'h201004) & memread)}} << (intClaim[1]-1)); + flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending); - // pending array - indexed by priority_lvl x source_ID - genvar i, j; - for (j=1; j<=7; j++) begin: pending - for (i=1; i<=N; i=i+1) begin: pendingbit - assign pendingArray[j][i] = (intPriority[i]==j) & intEn[i] & intPending[i]; + // context-dependent signals + genvar ctx; + for (ctx=0; ctx<`C; ctx++) begin + // request matrix + // priority level (rows) X source ID (columns) + // + // irqMatrix[ctx][pri][src] is high if source + // has priority level and has an "active" interrupt request + // ("active" meaning it is enabled in context and is pending) + genvar src, pri; + for (pri=1; pri<=7; pri++) begin + for (src=1; src<=`N; src++) begin + assign irqMatrix[ctx][pri][src] = (intPriority[src]==pri) & intPending[src] & intEn[ctx][src]; + end end - end - // pending array, except grouped by priority - assign pendingPGrouped[7:1] = {|pendingArray[7], - |pendingArray[6], - |pendingArray[5], - |pendingArray[4], - |pendingArray[3], - |pendingArray[2], - |pendingArray[1]}; - //assign pendingPGrouped = pendingArray.or; - // pendingPGrouped, except only topmost priority is active - assign pendingMaxP[7:1] = {pendingPGrouped[7], - pendingPGrouped[6] & ~|pendingPGrouped[7], - pendingPGrouped[5] & ~|pendingPGrouped[7:6], - pendingPGrouped[4] & ~|pendingPGrouped[7:5], - pendingPGrouped[3] & ~|pendingPGrouped[7:4], - pendingPGrouped[2] & ~|pendingPGrouped[7:3], - pendingPGrouped[1] & ~|pendingPGrouped[7:2]}; - // select the pending requests at that priority - assign pendingRequestsAtMaxP[N:1] = ({N{pendingMaxP[7]}} & pendingArray[7]) - | ({N{pendingMaxP[6]}} & pendingArray[6]) - | ({N{pendingMaxP[5]}} & pendingArray[5]) - | ({N{pendingMaxP[4]}} & pendingArray[4]) - | ({N{pendingMaxP[3]}} & pendingArray[3]) - | ({N{pendingMaxP[2]}} & pendingArray[2]) - | ({N{pendingMaxP[1]}} & pendingArray[1]); - // find the lowest ID amongst active interrupts at the highest priority - logic [5:0] k; - always_comb begin - intClaim = 6'b0; - for (k=N; k>0; k=k-1) begin - if (pendingRequestsAtMaxP[k]) intClaim = k; + // which prority levels have one or more active requests? + assign priorities_with_irqs[ctx][7:1] = { + |irqMatrix[ctx][7], + |irqMatrix[ctx][6], + |irqMatrix[ctx][5], + |irqMatrix[ctx][4], + |irqMatrix[ctx][3], + |irqMatrix[ctx][2], + |irqMatrix[ctx][1] + }; + + // get the highest priority level that has active requests + assign max_priority_with_irqs[ctx][7:1] = { + priorities_with_irqs[ctx][7], + priorities_with_irqs[ctx][6] & ~|priorities_with_irqs[ctx][7], + priorities_with_irqs[ctx][5] & ~|priorities_with_irqs[ctx][7:6], + priorities_with_irqs[ctx][4] & ~|priorities_with_irqs[ctx][7:5], + priorities_with_irqs[ctx][3] & ~|priorities_with_irqs[ctx][7:4], + priorities_with_irqs[ctx][2] & ~|priorities_with_irqs[ctx][7:3], + priorities_with_irqs[ctx][1] & ~|priorities_with_irqs[ctx][7:2] + }; + + // of the sources at the highest priority level that has active requests, + // which sources have active requests? + assign irqs_at_max_priority[ctx][`N:1] = + ({`N{max_priority_with_irqs[ctx][7]}} & irqMatrix[ctx][7]) | + ({`N{max_priority_with_irqs[ctx][6]}} & irqMatrix[ctx][6]) | + ({`N{max_priority_with_irqs[ctx][5]}} & irqMatrix[ctx][5]) | + ({`N{max_priority_with_irqs[ctx][4]}} & irqMatrix[ctx][4]) | + ({`N{max_priority_with_irqs[ctx][3]}} & irqMatrix[ctx][3]) | + ({`N{max_priority_with_irqs[ctx][2]}} & irqMatrix[ctx][2]) | + ({`N{max_priority_with_irqs[ctx][1]}} & irqMatrix[ctx][1]); + + // of the sources at the highest priority level that has active requests, + // choose the source with the lowest source ID to be the most urgent + // and set intClaim to the source ID of the most urgent active request + integer k; + always_comb begin + intClaim[ctx] = 6'b0; + for (k=`N; k>0; k--) begin + if (irqs_at_max_priority[ctx][k]) intClaim[ctx] = k[5:0]; + end end - end - - // create threshold mask - always_comb begin - threshMask[7] = (intThreshold != 7); - threshMask[6] = (intThreshold != 6) & threshMask[7]; - threshMask[5] = (intThreshold != 5) & threshMask[6]; - threshMask[4] = (intThreshold != 4) & threshMask[5]; - threshMask[3] = (intThreshold != 3) & threshMask[4]; - threshMask[2] = (intThreshold != 2) & threshMask[3]; - threshMask[1] = (intThreshold != 1) & threshMask[2]; - end - // is the max priority > threshold? - // *** would it be any better to first priority encode maxPriority into binary and then ">" with threshold? - assign ExtIntM = |(threshMask & pendingPGrouped); + + // create threshold mask + always_comb begin + threshMask[ctx][7] = (intThreshold[ctx] != 7); + threshMask[ctx][6] = (intThreshold[ctx] != 6) & threshMask[ctx][7]; + threshMask[ctx][5] = (intThreshold[ctx] != 5) & threshMask[ctx][6]; + threshMask[ctx][4] = (intThreshold[ctx] != 4) & threshMask[ctx][5]; + threshMask[ctx][3] = (intThreshold[ctx] != 3) & threshMask[ctx][4]; + threshMask[ctx][2] = (intThreshold[ctx] != 2) & threshMask[ctx][3]; + threshMask[ctx][1] = (intThreshold[ctx] != 1) & threshMask[ctx][2]; + end + // is the max priority > threshold? + // *** would it be any better to first priority encode maxPriority into binary and then ">" with threshold? + end + assign ExtIntM = |(threshMask[0] & priorities_with_irqs[0]); + assign ExtIntS = |(threshMask[1] & priorities_with_irqs[1]); endmodule diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index d90a30d7c..f48b96963 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -55,7 +55,7 @@ module uncore ( input logic [3:0] HSIZED, input logic HWRITED, // peripheral pins - output logic TimerIntM, SwIntM, ExtIntM, + output logic TimerIntM, SwIntM, ExtIntM, ExtIntS, input logic [31:0] GPIOPinsIn, output logic [31:0] GPIOPinsOut, GPIOPinsEn, input logic UARTSin, @@ -133,9 +133,10 @@ module uncore ( .HWRITE, .HREADY, .HTRANS, .HWDATA, .UARTIntr, .GPIOIntr, .HREADPLIC, .HRESPPLIC, .HREADYPLIC, - .ExtIntM); + .ExtIntM, .ExtIntS); end else begin : plic assign ExtIntM = 0; + assign ExtIntS = 0; end if (`GPIO_SUPPORTED == 1) begin : gpio gpio gpio( diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index c8be1116b..366ae2170 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -32,137 +32,137 @@ /* verilator lint_on UNUSED */ module wallypipelinedcore ( - input logic clk, reset, + input logic clk, reset, // Privileged - input logic TimerIntM, ExtIntM, SwIntM, - input logic [63:0] MTIME_CLINT, + input logic TimerIntM, ExtIntM, ExtIntS, SwIntM, + input logic [63:0] MTIME_CLINT, // Bus Interface input logic [`AHBW-1:0] HRDATA, - input logic HREADY, HRESP, - output logic HCLK, HRESETn, - output logic [31:0] HADDR, + input logic HREADY, HRESP, + output logic HCLK, HRESETn, + output logic [31:0] HADDR, output logic [`AHBW-1:0] HWDATA, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK, + output logic HWRITE, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [3:0] HPROT, + output logic [1:0] HTRANS, + output logic HMASTLOCK, // Delayed signals for subword write - output logic [2:0] HADDRD, - output logic [3:0] HSIZED, - output logic HWRITED + output logic [2:0] HADDRD, + output logic [3:0] HSIZED, + output logic HWRITED ); // logic [1:0] ForwardAE, ForwardBE; - logic StallF, StallD, StallE, StallM, StallW; - logic FlushF, FlushD, FlushE, FlushM, FlushW; - logic RetM; + logic StallF, StallD, StallE, StallM, StallW; + logic FlushF, FlushD, FlushE, FlushM, FlushW; + logic RetM; (* mark_debug = "true" *) logic TrapM; // new signals that must connect through DP - logic MDUE, W64E; - logic CSRReadM, CSRWriteM, PrivilegedM; - logic [1:0] AtomicE; - logic [1:0] AtomicM; - logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE; - logic [`XLEN-1:0] SrcAM; - logic [2:0] Funct3E; + logic MDUE, W64E; + logic CSRReadM, CSRWriteM, PrivilegedM; + logic [1:0] AtomicE; + logic [1:0] AtomicM; + logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE; + logic [`XLEN-1:0] SrcAM; + logic [2:0] Funct3E; // logic [31:0] InstrF; - logic [31:0] InstrD, InstrW; - (* mark_debug = "true" *) logic [31:0] InstrM; - logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE; - (* mark_debug = "true" *) logic [`XLEN-1:0] PCM; - logic [`XLEN-1:0] CSRReadValW, MDUResultW; - logic [`XLEN-1:0] PrivilegedNextPCM; - (* mark_debug = "true" *) logic [1:0] MemRWM; - (* mark_debug = "true" *) logic InstrValidM; - logic InstrMisalignedFaultM; - logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; - logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM; - logic LoadMisalignedFaultM, LoadAccessFaultM; - logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM; - logic [`XLEN-1:0] InstrMisalignedAdrM; + logic [31:0] InstrD, InstrW; + (* mark_debug = "true" *) logic [31:0] InstrM; + logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE; + (* mark_debug = "true" *) logic [`XLEN-1:0] PCM; + logic [`XLEN-1:0] CSRReadValW, MDUResultW; + logic [`XLEN-1:0] PrivilegedNextPCM; + (* mark_debug = "true" *) logic [1:0] MemRWM; + (* mark_debug = "true" *) logic InstrValidM; + logic InstrMisalignedFaultM; + logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; + logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM; + logic LoadMisalignedFaultM, LoadAccessFaultM; + logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM; + logic [`XLEN-1:0] InstrMisalignedAdrM; logic InvalidateICacheM, FlushDCacheM; - logic PCSrcE; - logic CSRWritePendingDEM; - logic DivBusyE; + logic PCSrcE; + logic CSRWritePendingDEM; + logic DivBusyE; logic DivE; - logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; - logic SquashSCW; + logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; + logic SquashSCW; // floating point unit signals - logic [2:0] FRM_REGW; + logic [2:0] FRM_REGW; logic [4:0] RdM, RdW; - logic FStallD; - logic FWriteIntE; - logic [`XLEN-1:0] FWriteDataE; - logic [`XLEN-1:0] FIntResM; - logic FDivBusyE; - logic IllegalFPUInstrD, IllegalFPUInstrE; - logic FRegWriteM; - logic FPUStallD; - logic [4:0] SetFflagsM; + logic FStallD; + logic FWriteIntE; + logic [`XLEN-1:0] FWriteDataE; + logic [`XLEN-1:0] FIntResM; + logic FDivBusyE; + logic IllegalFPUInstrD, IllegalFPUInstrE; + logic FRegWriteM; + logic FPUStallD; + logic [4:0] SetFflagsM; // memory management unit signals - logic ITLBWriteF; - logic ITLBFlushF, DTLBFlushM; - logic ITLBMissF; - logic [`XLEN-1:0] SATP_REGW; + logic ITLBWriteF; + logic ITLBFlushF, DTLBFlushM; + logic ITLBMissF; + logic [`XLEN-1:0] SATP_REGW; logic STATUS_MXR, STATUS_SUM, STATUS_MPRV; logic [1:0] STATUS_MPP; - logic [1:0] PrivilegeModeW; - logic [`XLEN-1:0] PTE; - logic [1:0] PageType; + logic [1:0] PrivilegeModeW; + logic [`XLEN-1:0] PTE; + logic [1:0] PageType; // PMA checker signals var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0]; var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0]; // IMem stalls - logic IFUStallF; - logic LSUStallM; + logic IFUStallF; + logic LSUStallM; // cpu lsu interface - logic [2:0] Funct3M; - logic [`XLEN-1:0] IEUAdrE; + logic [2:0] Funct3M; + logic [`XLEN-1:0] IEUAdrE; (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM; - (* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM; - (* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM; - logic [`XLEN-1:0] ReadDataW; - logic CommittedM; + (* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM; + (* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM; + logic [`XLEN-1:0] ReadDataW; + logic CommittedM; // AHB ifu interface - logic [`PA_BITS-1:0] IFUBusAdr; - logic [`XLEN-1:0] IFUBusHRDATA; - logic IFUBusRead; - logic IFUBusAck; + logic [`PA_BITS-1:0] IFUBusAdr; + logic [`XLEN-1:0] IFUBusHRDATA; + logic IFUBusRead; + logic IFUBusAck; // AHB LSU interface - logic [`PA_BITS-1:0] LSUBusAdr; - logic LSUBusRead; - logic LSUBusWrite; - logic LSUBusAck; - logic [`XLEN-1:0] LSUBusHRDATA; - logic [`XLEN-1:0] LSUBusHWDATA; + logic [`PA_BITS-1:0] LSUBusAdr; + logic LSUBusRead; + logic LSUBusWrite; + logic LSUBusAck; + logic [`XLEN-1:0] LSUBusHRDATA; + logic [`XLEN-1:0] LSUBusHWDATA; - logic BPPredWrongE; - logic BPPredDirWrongM; - logic BTBPredPCWrongM; - logic RASPredPCWrongM; - logic BPPredClassNonCFIWrongM; - logic [4:0] InstrClassM; - logic InstrAccessFaultF; - logic [2:0] LSUBusSize; + logic BPPredWrongE; + logic BPPredDirWrongM; + logic BTBPredPCWrongM; + logic RASPredPCWrongM; + logic BPPredClassNonCFIWrongM; + logic [4:0] InstrClassM; + logic InstrAccessFaultF; + logic [2:0] LSUBusSize; - logic ExceptionM; - logic PendingInterruptM; - logic DCacheMiss; - logic DCacheAccess; - logic ICacheMiss; - logic ICacheAccess; - logic BreakpointFaultM, EcallFaultM; + logic ExceptionM; + logic PendingInterruptM; + logic DCacheMiss; + logic DCacheAccess; + logic ICacheMiss; + logic ICacheAccess; + logic BreakpointFaultM, EcallFaultM; logic InstrDAPageFaultF; ifu ifu( @@ -203,8 +203,8 @@ module wallypipelinedcore ( .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrDAPageFaultF - - ); // instruction fetch unit: PC, branch prediction, instruction cache + + ); // instruction fetch unit: PC, branch prediction, instruction cache ieu ieu( .clk, .reset, @@ -221,7 +221,7 @@ module wallypipelinedcore ( // Memory stage interface .SquashSCW, // from LSU .MemRWM, // read/write control goes to LSU - .AtomicE, // atomic control goes to LSU + .AtomicE, // atomic control goes to LSU .AtomicM, // atomic control goes to LSU .WriteDataM, // Write data to LSU .Funct3M, // size and signedness to LSU @@ -245,41 +245,41 @@ module wallypipelinedcore ( lsu lsu( .clk, .reset, .StallM, .FlushM, .StallW, - .FlushW, - // CPU interface - .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), - .AtomicM, .TrapM, - .CommittedM, .DCacheMiss, .DCacheAccess, - .SquashSCW, - //.DataMisalignedM(DataMisalignedM), - .IEUAdrE, .IEUAdrM, .WriteDataM, - .ReadDataM, .FlushDCacheM, - // connected to ahb (all stay the same) - .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, - .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, + .FlushW, + // CPU interface + .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), + .AtomicM, .TrapM, + .CommittedM, .DCacheMiss, .DCacheAccess, + .SquashSCW, + //.DataMisalignedM(DataMisalignedM), + .IEUAdrE, .IEUAdrM, .WriteDataM, + .ReadDataM, .FlushDCacheM, + // connected to ahb (all stay the same) + .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, + .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, - // connect to csr or privilege and stay the same. - .PrivilegeModeW, // connects to csr - .PMPCFG_ARRAY_REGW, // connects to csr - .PMPADDR_ARRAY_REGW, // connects to csr - // hptw keep i/o - .SATP_REGW, // from csr - .STATUS_MXR, // from csr - .STATUS_SUM, // from csr - .STATUS_MPRV, // from csr - .STATUS_MPP, // from csr + // connect to csr or privilege and stay the same. + .PrivilegeModeW, // connects to csr + .PMPCFG_ARRAY_REGW, // connects to csr + .PMPADDR_ARRAY_REGW, // connects to csr + // hptw keep i/o + .SATP_REGW, // from csr + .STATUS_MXR, // from csr + .STATUS_SUM, // from csr + .STATUS_MPRV, // from csr + .STATUS_MPP, // from csr - .DTLBFlushM, // connects to privilege - .LoadPageFaultM, // connects to privilege - .StoreAmoPageFaultM, // connects to privilege - .LoadMisalignedFaultM, // connects to privilege - .LoadAccessFaultM, // connects to privilege - .StoreAmoMisalignedFaultM, // connects to privilege - .StoreAmoAccessFaultM, // connects to privilege + .DTLBFlushM, // connects to privilege + .LoadPageFaultM, // connects to privilege + .StoreAmoPageFaultM, // connects to privilege + .LoadMisalignedFaultM, // connects to privilege + .LoadAccessFaultM, // connects to privilege + .StoreAmoMisalignedFaultM, // connects to privilege + .StoreAmoAccessFaultM, // connects to privilege .InstrDAPageFaultF, - .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, - .LSUStallM); // change to LSUStallM + .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, + .LSUStallM); // change to LSUStallM // *** Ross: please make EBU conditional when only supporting internal memories @@ -306,13 +306,13 @@ module wallypipelinedcore ( .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD, .LSUStallM, .IFUStallF, .FPUStallD, .FStallD, - .DivBusyE, .FDivBusyE, - .EcallFaultM, .BreakpointFaultM, + .DivBusyE, .FDivBusyE, + .EcallFaultM, .BreakpointFaultM, .InvalidateICacheM, // Stall & flush outputs - .StallF, .StallD, .StallE, .StallM, .StallW, - .FlushF, .FlushD, .FlushE, .FlushM, .FlushW - ); // global stall and flush control + .StallF, .StallD, .StallE, .StallM, .StallW, + .FlushF, .FlushD, .FlushE, .FlushM, .FlushW + ); // global stall and flush control if (`ZICSR_SUPPORTED) begin:priv privileged priv( @@ -331,7 +331,7 @@ module wallypipelinedcore ( .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, - .TimerIntM, .ExtIntM, .SwIntM, + .TimerIntM, .ExtIntM, .ExtIntS, .SwIntM, .MTIME_CLINT, .InstrMisalignedAdrM, .IEUAdrM, .SetFflagsM, diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index 1b7f38311..0d844d3cf 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -74,7 +74,7 @@ module wallypipelinedsoc ( logic HRESP; logic TimerIntM, SwIntM; // from CLINT logic [63:0] MTIME_CLINT; // from CLINT to CSRs - logic ExtIntM; // from PLIC + logic ExtIntM,ExtIntS; // from PLIC logic [2:0] HADDRD; logic [3:0] HSIZED; logic HWRITED; @@ -84,7 +84,7 @@ module wallypipelinedsoc ( // instantiate processor and memories wallypipelinedcore core(.clk, .reset, - .TimerIntM, .ExtIntM, .SwIntM, + .TimerIntM, .ExtIntM, .ExtIntS, .SwIntM, .MTIME_CLINT, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, @@ -94,7 +94,7 @@ module wallypipelinedsoc ( uncore uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED, - .TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, + .TimerIntM, .SwIntM, .ExtIntM, .ExtIntS, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .HSELEXT, .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 62d13a1a3..8b37bcbc5 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -334,8 +334,8 @@ module testbench; //`INIT_CHECKPOINT_VAL(UART_MSR, [7:0]); `INIT_CHECKPOINT_VAL(UART_SCR, [7:0]); `INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1); - `INIT_CHECKPOINT_VAL(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1]); - `INIT_CHECKPOINT_VAL(PLIC_THRESHOLD, [2:0]); + `INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1],1,0); + `INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_THRESHOLD, [2:0],1,0); integer memFile; integer readResult;