mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Almost working with modelsim and verilator.
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d617eb0977
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@ -78,8 +78,8 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
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//assign HREADRam = HRDATA2 === 'bx ? 64'hdeadbeefdeadbeef : HRDATA2;
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// **** RT: MAJOR BUG can't leave in for anything. Will cause synthesis issues.
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// PRIV sv48-svadu test not working without it.
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assign HREADRam = HRDATA2 === 'bx ? 64'h0 : HRDATA2;
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//assign HREADRam = HRDATA2;
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//assign HREADRam = HRDATA2 === 'bx ? 64'h0 : HRDATA2;
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assign HREADRam = HRDATA2;
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// use this to add arbitrary latency to ram. Helps test AHB controller correctness
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if(`RAM_LATENCY > 0) begin
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@ -85,7 +85,7 @@ module testbench;
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logic riscofTest;
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logic Validate;
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logic SelectTest;
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logic TestComplete;
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// pick tests based on modes supported
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initial begin
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@ -176,7 +176,6 @@ module testbench;
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STATE_LOAD_MEMORIES,
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STATE_RESET_TEST,
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STATE_RUN_TEST,
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STATE_COPY_RAM,
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STATE_CHECK_TEST,
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STATE_CHECK_TEST_WAIT,
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STATE_VALIDATE,
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@ -219,9 +218,8 @@ module testbench;
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STATE_LOAD_MEMORIES: NextState = STATE_RESET_TEST;
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STATE_RESET_TEST: if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST;
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else NextState = STATE_RUN_TEST;
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STATE_RUN_TEST: if(TestComplete) NextState = STATE_COPY_RAM;
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STATE_RUN_TEST: if(DCacheFlushStart) NextState = STATE_CHECK_TEST;
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else NextState = STATE_RUN_TEST;
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STATE_COPY_RAM: NextState = STATE_CHECK_TEST;
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STATE_CHECK_TEST: if (DCacheFlushDone) NextState = STATE_VALIDATE;
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else NextState = STATE_CHECK_TEST_WAIT;
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STATE_CHECK_TEST_WAIT: if(DCacheFlushDone) NextState = STATE_VALIDATE;
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@ -242,8 +240,6 @@ module testbench;
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assign ResetCntEn = CurrState == STATE_RESET_TEST;
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assign Validate = CurrState == STATE_VALIDATE;
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assign SelectTest = CurrState == STATE_INIT_TEST;
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assign CopyRAM = TestComplete & CurrState == STATE_RUN_TEST;
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assign DCacheFlushStart = CurrState == STATE_COPY_RAM;
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// fsm reset counter
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counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount);
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@ -275,7 +271,7 @@ module testbench;
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////////////////////////////////////////////////////////////////////////////////
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if(TestBenchReset) test = 1;
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if (TEST == "coremark")
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if (dut.core.priv.priv.EcallFaultM) begin
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if (dut.core.EcallFaultM) begin
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$display("Benchmark: coremark is done.");
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$stop;
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end
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@ -324,7 +320,6 @@ module testbench;
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////////////////////////////////////////////////////////////////////////////////
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// Some memories are not reset, but should be zeros or set to some initial value for simulation
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////////////////////////////////////////////////////////////////////////////////
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/* -----\/----- EXCLUDED -----\/-----
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integer adrindex;
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always @(posedge clk) begin
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if (ResetMem) // program memory is sometimes reset
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@ -344,50 +339,13 @@ module testbench;
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end
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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// still not working in this format
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/* -----\/----- EXCLUDED -----\/-----
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integer adrindex;
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if (P.UNCORE_RAM_SUPPORTED) begin
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always @(posedge clk) begin
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if (ResetMem) // program memory is sometimes reset
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for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
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dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
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end
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end
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genvar adrindex2;
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if (P.BPRED_SUPPORTED & (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)) begin
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for(adrindex2 = 0; adrindex2 < 2**P.BPRED_NUM_LHR; adrindex2++)
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always @(posedge clk) begin
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dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex2] = 0;
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end
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end
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if (P.BPRED_SUPPORTED) begin
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always @(posedge clk)
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dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[0] = 0;
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for(adrindex2 = 0; adrindex2 < 2**P.BTB_SIZE; adrindex2++)
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always @(posedge clk) begin
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dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex2] = 0;
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end
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for(adrindex2 = 0; adrindex2 < 2**P.BPRED_SIZE; adrindex2++)
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always @(posedge clk) begin
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dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex2] = 0;
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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////////////////////////////////////////////////////////////////////////////////
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// load memories with program image
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////////////////////////////////////////////////////////////////////////////////
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integer IndexTemp;
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if (P.SDC_SUPPORTED) begin
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always @(posedge clk) begin
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if (LoadMem) begin
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if (P.SDC_SUPPORTED) begin
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string romfilename, sdcfilename;
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romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
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sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
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@ -396,39 +354,11 @@ module testbench;
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// shorten sdc timers for simulation
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//dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
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end
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end
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end else if (P.IROM_SUPPORTED) begin
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always @(posedge clk) begin
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if (LoadMem) begin
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$readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
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end
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end
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end else if (P.BUS_SUPPORTED) begin
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always @(posedge clk) begin
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if (LoadMem) begin
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$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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end
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if (CopyRAM) begin
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for(IndexTemp = 0; IndexTemp < (P.UNCORE_RAM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin
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//if(dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests.
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testbench.DCacheFlushFSM.ShadowRAM[((P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp];
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end
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end
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end
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end
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if (P.DTIM_SUPPORTED) begin
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always @(posedge clk) begin
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if (LoadMem) begin
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$readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
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else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
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else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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if (P.DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
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$display("Read memfile %s", memfilename);
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end
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if (CopyRAM) begin
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for(IndexTemp = 0; IndexTemp < (P.DTIM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin
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//if(dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests.
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testbench.DCacheFlushFSM.ShadowRAM[((P.DTIM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp];
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end
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end
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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@ -519,14 +449,13 @@ module testbench;
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logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
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if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
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else assign ecf = 0;
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assign TestComplete = ecf &
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assign DCacheFlushStart = ecf &
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(dut.core.ieu.dp.regf.rf[3] == 1 |
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(dut.core.ieu.dp.regf.we3 &
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dut.core.ieu.dp.regf.a3 == 3 &
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dut.core.ieu.dp.regf.wd3 == 1)) |
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((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
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((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
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//assign DCacheFlushStart = TestComplete;
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DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
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@ -579,24 +508,15 @@ module testbench;
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testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
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testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
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/* verilator lint_off INFINITELOOP */
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/* verilator lint_off WIDTHXZEXPAND */
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while (signature[i] !== 'bx) begin
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/* verilator lint_on WIDTHXZEXPAND */
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logic [P.XLEN-1:0] sig;
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// **************************************
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// ***** BUG BUG BUG make sure RT undoes this.
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//if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
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//else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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//if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
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else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
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//if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin
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if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin
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if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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//$display(" Error on test %s result %d: adr = %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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// TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]);
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$stop; //***debug
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end
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i = i + 1;
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