From 9ee1ffe8fe1fd79023f64e1829d91f007af3113c Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 20 Dec 2023 11:29:31 -0600 Subject: [PATCH] Almost working with modelsim and verilator. --- src/uncore/ram_ahb.sv | 4 +- testbench/testbench.sv | 116 +++++++---------------------------------- 2 files changed, 20 insertions(+), 100 deletions(-) diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 6c16c675d..f78998d9d 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -78,8 +78,8 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, //assign HREADRam = HRDATA2 === 'bx ? 64'hdeadbeefdeadbeef : HRDATA2; // **** RT: MAJOR BUG can't leave in for anything. Will cause synthesis issues. // PRIV sv48-svadu test not working without it. - assign HREADRam = HRDATA2 === 'bx ? 64'h0 : HRDATA2; - //assign HREADRam = HRDATA2; + //assign HREADRam = HRDATA2 === 'bx ? 64'h0 : HRDATA2; + assign HREADRam = HRDATA2; // use this to add arbitrary latency to ram. Helps test AHB controller correctness if(`RAM_LATENCY > 0) begin diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 3607a5f06..ece7500d5 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -85,7 +85,7 @@ module testbench; logic riscofTest; logic Validate; logic SelectTest; - logic TestComplete; + // pick tests based on modes supported initial begin @@ -176,7 +176,6 @@ module testbench; STATE_LOAD_MEMORIES, STATE_RESET_TEST, STATE_RUN_TEST, - STATE_COPY_RAM, STATE_CHECK_TEST, STATE_CHECK_TEST_WAIT, STATE_VALIDATE, @@ -219,9 +218,8 @@ module testbench; STATE_LOAD_MEMORIES: NextState = STATE_RESET_TEST; STATE_RESET_TEST: if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST; else NextState = STATE_RUN_TEST; - STATE_RUN_TEST: if(TestComplete) NextState = STATE_COPY_RAM; + STATE_RUN_TEST: if(DCacheFlushStart) NextState = STATE_CHECK_TEST; else NextState = STATE_RUN_TEST; - STATE_COPY_RAM: NextState = STATE_CHECK_TEST; STATE_CHECK_TEST: if (DCacheFlushDone) NextState = STATE_VALIDATE; else NextState = STATE_CHECK_TEST_WAIT; STATE_CHECK_TEST_WAIT: if(DCacheFlushDone) NextState = STATE_VALIDATE; @@ -242,8 +240,6 @@ module testbench; assign ResetCntEn = CurrState == STATE_RESET_TEST; assign Validate = CurrState == STATE_VALIDATE; assign SelectTest = CurrState == STATE_INIT_TEST; - assign CopyRAM = TestComplete & CurrState == STATE_RUN_TEST; - assign DCacheFlushStart = CurrState == STATE_COPY_RAM; // fsm reset counter counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount); @@ -275,7 +271,7 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// if(TestBenchReset) test = 1; if (TEST == "coremark") - if (dut.core.priv.priv.EcallFaultM) begin + if (dut.core.EcallFaultM) begin $display("Benchmark: coremark is done."); $stop; end @@ -324,7 +320,6 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// // Some memories are not reset, but should be zeros or set to some initial value for simulation //////////////////////////////////////////////////////////////////////////////// -/* -----\/----- EXCLUDED -----\/----- integer adrindex; always @(posedge clk) begin if (ResetMem) // program memory is sometimes reset @@ -344,50 +339,13 @@ module testbench; end end end - -----/\----- EXCLUDED -----/\----- */ - // still not working in this format -/* -----\/----- EXCLUDED -----\/----- - integer adrindex; - if (P.UNCORE_RAM_SUPPORTED) begin - always @(posedge clk) begin - if (ResetMem) // program memory is sometimes reset - for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; - end - end - - genvar adrindex2; - - if (P.BPRED_SUPPORTED & (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)) begin - for(adrindex2 = 0; adrindex2 < 2**P.BPRED_NUM_LHR; adrindex2++) - always @(posedge clk) begin - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex2] = 0; - end - end - - if (P.BPRED_SUPPORTED) begin - always @(posedge clk) - dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[0] = 0; - for(adrindex2 = 0; adrindex2 < 2**P.BTB_SIZE; adrindex2++) - always @(posedge clk) begin - dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex2] = 0; - end - for(adrindex2 = 0; adrindex2 < 2**P.BPRED_SIZE; adrindex2++) - always @(posedge clk) begin - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex2] = 0; - end - end - -----/\----- EXCLUDED -----/\----- */ - //////////////////////////////////////////////////////////////////////////////// // load memories with program image //////////////////////////////////////////////////////////////////////////////// - - integer IndexTemp; - if (P.SDC_SUPPORTED) begin - always @(posedge clk) begin - if (LoadMem) begin + always @(posedge clk) begin + if (LoadMem) begin + if (P.SDC_SUPPORTED) begin string romfilename, sdcfilename; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; @@ -395,41 +353,13 @@ module testbench; //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem); // shorten sdc timers for simulation //dut.uncore.uncore.sdc.SDC.LimitTimers = 1; - end + end + else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); + else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + if (P.DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + $display("Read memfile %s", memfilename); end - end else if (P.IROM_SUPPORTED) begin - always @(posedge clk) begin - if (LoadMem) begin - $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); - end - end - end else if (P.BUS_SUPPORTED) begin - always @(posedge clk) begin - if (LoadMem) begin - $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - end - if (CopyRAM) begin - for(IndexTemp = 0; IndexTemp < (P.UNCORE_RAM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin - //if(dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests. - testbench.DCacheFlushFSM.ShadowRAM[((P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.uncore.uncore.ram.ram.memory.RAM[IndexTemp]; - end - end - end - end - if (P.DTIM_SUPPORTED) begin - always @(posedge clk) begin - if (LoadMem) begin - $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); - $display("Read memfile %s", memfilename); - end - if (CopyRAM) begin - for(IndexTemp = 0; IndexTemp < (P.DTIM_RANGE)>>1+(P.XLEN/32); IndexTemp++) begin - //if(dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp] === 'bx) break; // end copy early if at the end of the sig *** double check this will be valid for all tests. - testbench.DCacheFlushFSM.ShadowRAM[((P.DTIM_BASE)>>1+(P.XLEN/32)) + IndexTemp] = dut.core.lsu.dtim.dtim.ram.RAM[IndexTemp]; - end - end - end - end + end //////////////////////////////////////////////////////////////////////////////// // Actual hardware @@ -519,15 +449,14 @@ module testbench; logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM; else assign ecf = 0; - assign TestComplete = ecf & + assign DCacheFlushStart = ecf & (dut.core.ieu.dp.regf.rf[3] == 1 | (dut.core.ieu.dp.regf.we3 & dut.core.ieu.dp.regf.a3 == 3 & dut.core.ieu.dp.regf.wd3 == 1)) | ((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) | - ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); - //assign DCacheFlushStart = TestComplete; - + ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); + DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); task automatic CheckSignature; @@ -579,24 +508,15 @@ module testbench; testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8); testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8); /* verilator lint_off INFINITELOOP */ - /* verilator lint_off WIDTHXZEXPAND */ while (signature[i] !== 'bx) begin - /* verilator lint_on WIDTHXZEXPAND */ logic [P.XLEN-1:0] sig; - // ************************************** - // ***** BUG BUG BUG make sure RT undoes this. - //if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; - //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; - if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; - //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; + else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //$display("signature[%h] = %h sig = %h", i, signature[i], sig); - //if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin - if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin + if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin errors = errors+1; $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); - //$display(" Error on test %s result %d: adr = %h sim (DTIM_SUPPORTED) = %h, signature = %h", - // TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]); $stop; //***debug end i = i + 1;